ASIC Design Engineer – DSP, Optical Transmission

Mechanical EngineerMechanical EngineerFull TimeRemoteSeniorTeam 5,001-10,000Since 1985H1B SponsorCompany SiteLinkedIn

Location

Germany

Posted

78 days ago

Salary

0

Seniority

Senior

3 yrs expGermanEnglish

Job Description

ASIC Design Engineer – DSP, Optical Transmission

Ciena

• Propose innovative digital design solutions to develop power‑ and area‑optimized functional blocks for the Wavelogic product family • Collaborate with leading architects, systems engineers, and verification experts to bring complex, high‑speed digital designs to life • Interpret architecture and functional requirements to define and refine digital design specifications • Develop, integrate, and optimize RTL and C/C++ models to enable high‑performance, power‑efficient hardware blocks • Partner closely with systems, analog, and verification teams to validate functionality and enhance overall design robustness • Support simulation, regression debugging, and verification coverage closure • Contribute technical insights, assertions, and reviews that strengthen design quality and reduce development risk • Participate in lab validation activities for prototypes and product builds • Maintain clear tracking of issues and communicate progress to project stakeholders.

Job Requirements

  • 3+ years of experience in digital design for complex hardware circuits
  • MEng/MSc degree in electrical engineering, computer engineering, computer science, or related technical discipline
  • Hands‑on expertise with C++ development for High‑Level Synthesis (HLS)
  • Proficiency in generating RTL from C++ models using CatapultC or Stratus
  • Strong knowledge of SystemVerilog for RTL implementation
  • Solid understanding of timing, power, and area trade‑offs in hardware design
  • Effective communication and collaboration skills, including basic German language capability

Benefits

  • Flexible work environment
  • Professional growth opportunities
  • Meaningful social, community, and societal impact

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