Marvell Technology

• supporting and executing key aspects of Marvell's global export compliance program • supporting classification of products, software, and technology under applicable U.S. and international export and customs regulations • overseeing day-to-day management of the visitor policy • managing deemed export system • supporting trade due diligence efforts • maintaining compliance processes, training, audit and self-assessment programs • supporting implementation of program enhancements when needed

• Collaborate closely with the U.S.-based design team, local Taiwan product engineers, and overseas contract manufacturers to drive new product introduction into high-volume manufacturing. • Lead product and process transfers to overseas CMs. • Partner with overseas CMs to develop and enhance process capabilities for next-generation products.

• Plan and conduct on-site one-on-one listening sessions with employees across levels, functions, and geographies. • Build trust quickly and facilitate conversations in a neutral, non-leading manner; ask effective follow-up questions to clarify themes and root causes. • Maintain strict confidentiality and protect anonymity in all notes, summaries, and communications. • Identify themes, trends, and potential hotspots across multiple sessions; distinguish isolated feedback from consistent patterns. • Draft confidential, executive reports that summarize key themes and include de-identified verbatim comments. • Escalate significant legal, compliance, ethics, or safety matters via established channels, while balancing confidentiality requirements. • Partner with relevant stakeholders (e.g., BU executives, HR, Legal, Compliance, EHS, Security) as needed to ensure appropriate follow-up. • Manage session logistics end-to-end (scheduling, travel coordination inputs, intake tracking, and follow-up requests). • Continuously improve the listening-session approach and reporting templates based on feedback and outcomes.

• Design and develop high-speed EVK hardware to support optical validation of multiple DSP products for data-center connectivity • Review and drive high-quality schematics with attention to signal integrity, power integrity, and manufacturability • Work closely with PCB layout engineers to ensure compliance with high-speed design best practices • Plan and execute board builds, including component selection, procurement coordination, and build readiness • Lead hardware bring-up, debugging, and validation using lab equipment such as oscilloscopes, TDRs, and related measurement tools

• responsible for export and import compliance activities at all locations where Marvell conducts business • provide trade compliance support to U.S. and international operations • ensure business transactions are processed in compliance with applicable trade control requirements • support Marvell’s Global Export and Import Compliance Program • work closely with engineering, operations, shipping and logistics, and G&A functions across Marvell’s global locations • partner with stakeholders across the business to help navigate complex trade regulatory requirements • help ensure compliance with the Export Administration Regulations, OFAC sanctions, ITAR, U.S. customs requirements, and other applicable trade control regimes • establish and maintain compliance protocols, training, audit and self-assessment programs, and related documentation

• Align customer design requirements with our technology and assist with proposal development • Identify design opportunities • Guide customers through their design process • Provide SI/PI reviews (topology/vias/return paths, decap strategy, S-params) and recommend design fixes; coordinate simulations and correlate lab vs. model • Provide onsite support, and solving real time problems including software tool issues, HW and SW debugging, system bring-up issues • Train customers and distributor’s FAEs

• lead micro-architecture and RTL development and HW/SW co-design efforts • define ASIC and/or block architecture, micro-architecture and register specification • conduct detailed architectural and/or design requirement reviews with customers, cross-functional teams, IP Vendors • implement a specification using RTL coding techniques and best practices • work with the physical design teams, reviewing and providing guidance in floorplanning, power analysis, synthesis and timing signoff • work with the Verification team on pre-silicon verification tasks such as reviewing the verification test plans, coverage analysis, full-chip simulation, performance analysis and debug • help develop and/or evaluate design and verification methodologies and participate in improving existing ones • provide mentorship to the more junior team members

• Work on verification of memory, AI/HPC or Die-2-Die subsystems of Marvell's AI/ML, Network processing, Compute, Memory Expander and Accelerated Compute SOCs and IPs • Develop the architecture for a functional verification environment, including reference models and bus-functional monitors and drivers using System Verilog and UVM methodology • Analyze designs and architectures to develop test strategies that will ensure functional correctness • Develop verification testplan and write tests using random techniques and coverage analysis, and work with designers to ensure it is complete • Debug failures and work with designers to resolve issues • Contribute to the development and future direction of SoC verification methodologies and environments • Provide leadership for a geographically dispersed team of verification professionals in pre-silicon validation of a highly complex SoC design

• Collaborating with various teams to develop strategies • Pushing the IP roadmap and supporting multiple SoCs • Provide leadership in the development of highest value-add IP & SoC plans • Manage and continue to build a team of complex sub-system, co-processors, accelerator and SoC engineers • Develop methodologies and infrastructure • Work with architecture, SoCs, software, firmware, program management and post-silicon design teams for plan development and execution • Provide technical mentoring for team members • Actively engage in efforts to find improvements in methodologies, techniques, and automation

• Lead DV, emulation and post silicon validation execution with zero defect mindset • Define DV, emulation and post silicon validation scope • Define execution timelines working closely with stakeholders • Set goals, monitor, and take steps to keep the execution on track • Define DV methodology and verification strategies • Drive definition and implementation of DV TB architectures • Collaborate with Architecture, Design, DFT, PD, FW and system teams for successful product execution • Lead tool evaluation and selection • Drive continuous productivity improvements through incremental and forklift changes • Monitoring industry DV trends and adapting to key trends • Hire, build and retain high performance engineering team • Address continuous training and development needs of the team