EnCharge AI

Role Description As a Staff / Senior Staff CAD & Methodology Engineer, you will be the resident expert in Innovus and Tempus, responsible for developing, debugging, and continually accelerating our RTL-to-GDSII and timing signoff flows. You will work closely with Physical Design and STA leads to eliminate bottlenecks, automate manual tasks, and push the limits of EDA capabilities at advanced process nodes. Key Responsibilities - Flow Architecture & Automation: Architect, develop, and maintain a highly automated, robust, and scalable physical design and signoff flow from synthesis through GDSII, optimized for AI accelerator architectures. - Innovus Methodology: Drive advanced physical design methodologies in Cadence Innovus. Optimize recipes for floorplanning, placement, Clock Tree Synthesis (CTS), routing, and power grid implementation to squeeze out maximum PPA. - Tempus Signoff Integration: Own the STA and timing signoff methodology using Cadence Tempus. Implement and optimize Distributed Multi-Scenario Analysis (DMSA), advanced OCV methodologies, and automated Tempus ECO flows to ensure rapid timing closure. - Turnaround Time (TAT) Reduction: Identify inefficiencies in the daily execution of block and top-level implementation. Develop Python and Tcl-based automation, database parsers, and custom utilities to drastically reduce tool runtime and engineering debug time. - Tool & Vendor Interface: Act as the primary technical liaison with Cadence. Drive tool evaluations, beta testing of new features, and resolution of critical tool bugs or limitations to ensure continuous flow stability. - Mentorship & Support: Serve as the final escalation point for the PD and Timing teams regarding flow-related issues. Document methodologies clearly and mentor junior engineers on tool usage and flow mechanics. Qualifications - Experience: 9 to 14 years of industry experience in ASIC/SOC physical design, with a primary focus on CAD, TFM (Tools, Flows, and Methodology), or flow automation. - Cadence Mastery: Deep, production-proven expertise with Cadence Innovus (Implementation) and Cadence Tempus (Signoff STA). Strong understanding of internal tool mechanics, database access commands (dbGet), and advanced tool configuration. - Scripting & Software Skills: Expert-level proficiency in Tcl and Python. Strong background in Makefile generation, shell scripting, and version control (Git/Perforce). - Domain Knowledge: Thorough understanding of deep sub-micron physical design concepts (advanced node DRCs, cross-talk, electromigration, IR drop) and the theoretical foundations of Static Timing Analysis. - Startup Mindset: Ability to thrive in a fast-paced, dynamic environment where flow requirements evolve rapidly as the architecture matures. - Education: Bachelor’s or Master’s degree in Electrical Engineering, Computer Science, Computer Engineering, or a related discipline.

• Execute and manage the monthly, quarterly, and annual financial close process, ensuring timely and accurate completion of all accounting activities. • Prepare and review account reconciliations, ensuring accuracy, completeness, and appropriate supporting documentation. • Review and approve journal entries prepared by internal team members, outsourced accounting providers, or other stakeholders. • Maintain the integrity of the general ledger and ensure compliance with U.S. GAAP and company accounting policies. • Prepare and analyze monthly financial statements, including balance sheet, income statement, and cash flow reporting. • Coordinate and support external audits, and other regulatory reporting requirements. • Assist with grant applications, supplier proposals, and other financial reviews as needed. • Drive the adoption of AI-powered tools and automation within the accounting function, proactively identifying opportunities to improve close processes, account reconciliations, internal controls, and operational workflows while maintaining appropriate governance and accuracy. • Identify opportunities to improve accounting processes, internal controls, and system efficiencies. • Support implementation and optimization of ERP and other accounting systems. • Document accounting policies, procedures, and internal control processes. • Provide mentorship and guidance to accounting staff, contractors, or outsourced accounting teams as the organization grows. • Perform ad hoc financial analysis and special projects as assigned.

• Research and implement state-of-the-art techniques to accelerate AI inference • Partner closely with hardware, compiler, and quantization teams • Build profiling tools and comprehensive benchmarking frameworks • Build robust fine-tuning workflows for modern AI models

• Architect, design, and implement optimizations for AI model execution on graph compilers to improve performance, reduce latency, and maximize hardware utilization. • Work closely with ML researchers, hardware engineers, and software developers to design and deploy AI models, understanding and addressing hardware-specific challenges. • Work on performance optimizations for neural network models, such as layer fusion, operator fusion, and graph-level transformations. • Develop compiler optimizations and passes that convert high-level AI models (e.g., from TensorFlow, PyTorch) into intermediate representations (IR). • Implement parsing, semantic analysis, and IR generation for deep learning frameworks. • Research and integrate the latest advancements in compiler design, ML model optimizations, and hardware acceleration into graph compilers. • Provide leadership, mentorship, and technical guidance to a team of engineers focused on graph compiler optimizations.

• Lead the evaluation, selection, and implementation of a new HRIS platform, including requirements gathering, vendor selection, system design, testing, data migration, and successful go-live execution • Manage full HRIS implementation project lifecycle, including timelines, stakeholder coordination, risk management, and change management planning • Partner with HR, IT, Finance, and business leaders to ensure the HRIS aligns with organizational needs and long-term people strategy • Oversee system administration post-implementation, including user access management, security roles, and ongoing system configuration • Ensure ongoing HRIS data integrity through audits, governance standards, and data quality controls across all HR modules • Develop, maintain, and optimize HR reporting and analytics, including dashboards, standard reports, and ad hoc leadership requests • Continuously improve HR processes by identifying automation opportunities, configuring workflows, and enhancing system functionality • Provide end-user support, training, and documentation to HR teams, managers, and employees to ensure effective system adoption • Manage integrations between HRIS and other company systems (e.g., ATS, finance, benefits) and coordinate vendor relationships and upgrades • Ensure compliance with data privacy, security standards, and audit requirements while supporting internal and external audit requests

• Deploy and optimize LLMs (GPT, LLaMA, Mistral, Falcon, etc.) post-training from libraries like HuggingFace • Utilize inference runtimes such as ONNX Runtime, vLLM for efficient execution. • Optimize batching, caching, and tensor parallelism to improve LLM scalability in real-time applications. • Develop and maintain high-performance inference pipelines using Docker, Kubernetes, and other inference servers.

• Manage end-to-end onboarding, including offer acceptance, cross-functional setup (IT/Finance), and first-day readiness for new hires • Maintaining accurate employee records, processing changes • Provide support on immigration matters, including coordination and documentation • Administer HR programs and initiatives, supporting execution and continuous process improvements • Support performance management cycles, including goal setting, reviews, and compensation planning processes • Assist with global payroll operations, including data validation, tracking compensation changes, and supporting issue resolution • HR Recruiting support as needed - Coordinate and schedule interviews, ensuring a smooth and timely candidate experience across stakeholders and multiple time zones

• Define and develop the spec, architecture, and micro-architecture of key architecture modules (such as the in-memory compute unit, on-chip network, and memory orchestration units) based on the requirements of the workloads and software deployment flow • Contribute to the modeling of aforementioned key architecture modules in our C++ simulation framework to ensure a functional implementation of the features • Collaborate with the design verification team to deliver a strategy and infrastructure for the testing of the architecture features within said modules • Work with the software team and other architects to analyze the performance and efficiency of the architecture modules for key workloads, identify performance bottlenecks, and guide architectural decisions • Stay up to date with the latest trends and research in AI workloads, architectures, and applications to help define a path for the future generations of architectures

Role Description At EnCharge AI, we are building the next generation of AI compute silicon — purpose-built for high-performance, low-power, and scalable AI inference. As an Emulation Engineer, you will play a critical role in validating complex AI accelerator architectures on emulation platforms before tape-out. This position is ideal for someone passionate about bridging the gap between hardware and software in fast-paced, deep tech environments. - Set up and maintain Siemens Veloce emulation and prototyping platforms - Adapt SoC designs for Emulation and Prototyping - Develop and debug emulation testbenches and system-level environments - Support pre-silicon validation, power/performance analysis, and early software bring-up. Participate in silicon bring-up and validation. - Collaborate with design and verification teams to isolate design issues and accelerate debug. - Optimize performance of the emulation workloads and reduce turnaround time. - Work with firmware/software teams to enable use of emulators for OS and driver testing. Qualifications - BS/MS/Ph.D. in EE, CS, or related field with 7+ years of SoC design experience. - Experience with emulation platforms (Veloce, Palladium, or ZeBu) and FPGA-based prototyping systems (proFPGA, HAPS, or Protium) - Experience with emulating high speed I/O interfaces such as PCIe and UCIe and memory technologies such as LPDDR and HBM - Solid understanding of digital design, RTL (Verilog/SystemVerilog), and SoC architecture. - Proficiency in hardware debug tools, waveform viewers, and logic analyzers - Scripting skills (e.g., Python, Tcl, Perl) for automation and infrastructure development - Familiarity with UVM, simulation, and testbench environments. SystemVerilog and UVM-based verification experience a plus - Hand-on software development experience with C/C++ is a plus

• Coordinate transitioning tests from the lab environment to the production environment • Develop, debug, qualify, and deploy test programs to meet and exceed evolving customer needs and expectations • Drive yield optimization activities and improvements • Control the company’s RMA procedures and process. • Work with marketing teams to provide a first line of defense for yield loss, RMA and customer returns. • Drive failure analysis activities, investigating and solving complex issues in a fast-paced test department. • Designing experiments and analyzing data to root cause and debug product failures • Provide primary interface between the company and external semiconductor vendors (OSATs, foundries etc.) • Lead cross-functional teams in operations, engineering, and quality assurance to meet production targets and KPIs. • Collaborate with Supply Chain and Planning to develop and execute efficient production schedules based on customer demand and inventory goals. • Develop, manage, and execute qualification activities, including prototyping parts, engineering samples and qualification builds. • Coordinate Supply Chain Planning, Procurement and Sales Operations to support product development and manufacturing ramp‑up. • Oversee Bill of Materials (BOM) accuracy and SKU management • Maintain and update internal systems to reflect NPI/engineering demand, assembly instructions, build requirements, and engineering sample plans. • Lead continuous improvement initiatives to advance operational modeling, automation, and cost‑reduction opportunities.