EnCharge AI

• Deploy and optimize LLMs (GPT, LLaMA, Mistral, Falcon, etc.) post-training from libraries like HuggingFace • Utilize inference runtimes such as ONNX Runtime, vLLM for efficient execution. • Optimize batching, caching, and tensor parallelism to improve LLM scalability in real-time applications. • Develop and maintain high-performance inference pipelines using Docker, Kubernetes, and other inference servers.

• Manage end-to-end onboarding, including offer acceptance, cross-functional setup (IT/Finance), and first-day readiness for new hires • Maintaining accurate employee records, processing changes • Provide support on immigration matters, including coordination and documentation • Administer HR programs and initiatives, supporting execution and continuous process improvements • Support performance management cycles, including goal setting, reviews, and compensation planning processes • Assist with global payroll operations, including data validation, tracking compensation changes, and supporting issue resolution • HR Recruiting support as needed - Coordinate and schedule interviews, ensuring a smooth and timely candidate experience across stakeholders and multiple time zones

• Define and develop the spec, architecture, and micro-architecture of key architecture modules (such as the in-memory compute unit, on-chip network, and memory orchestration units) based on the requirements of the workloads and software deployment flow • Contribute to the modeling of aforementioned key architecture modules in our C++ simulation framework to ensure a functional implementation of the features • Collaborate with the design verification team to deliver a strategy and infrastructure for the testing of the architecture features within said modules • Work with the software team and other architects to analyze the performance and efficiency of the architecture modules for key workloads, identify performance bottlenecks, and guide architectural decisions • Stay up to date with the latest trends and research in AI workloads, architectures, and applications to help define a path for the future generations of architectures

Role Description At EnCharge AI, we are building the next generation of AI compute silicon — purpose-built for high-performance, low-power, and scalable AI inference. As an Emulation Engineer, you will play a critical role in validating complex AI accelerator architectures on emulation platforms before tape-out. This position is ideal for someone passionate about bridging the gap between hardware and software in fast-paced, deep tech environments. - Set up and maintain Siemens Veloce emulation and prototyping platforms - Adapt SoC designs for Emulation and Prototyping - Develop and debug emulation testbenches and system-level environments - Support pre-silicon validation, power/performance analysis, and early software bring-up. Participate in silicon bring-up and validation. - Collaborate with design and verification teams to isolate design issues and accelerate debug. - Optimize performance of the emulation workloads and reduce turnaround time. - Work with firmware/software teams to enable use of emulators for OS and driver testing. Qualifications - BS/MS/Ph.D. in EE, CS, or related field with 7+ years of SoC design experience. - Experience with emulation platforms (Veloce, Palladium, or ZeBu) and FPGA-based prototyping systems (proFPGA, HAPS, or Protium) - Experience with emulating high speed I/O interfaces such as PCIe and UCIe and memory technologies such as LPDDR and HBM - Solid understanding of digital design, RTL (Verilog/SystemVerilog), and SoC architecture. - Proficiency in hardware debug tools, waveform viewers, and logic analyzers - Scripting skills (e.g., Python, Tcl, Perl) for automation and infrastructure development - Familiarity with UVM, simulation, and testbench environments. SystemVerilog and UVM-based verification experience a plus - Hand-on software development experience with C/C++ is a plus

• Coordinate transitioning tests from the lab environment to the production environment • Develop, debug, qualify, and deploy test programs to meet and exceed evolving customer needs and expectations • Drive yield optimization activities and improvements • Control the company’s RMA procedures and process. • Work with marketing teams to provide a first line of defense for yield loss, RMA and customer returns. • Drive failure analysis activities, investigating and solving complex issues in a fast-paced test department. • Designing experiments and analyzing data to root cause and debug product failures • Provide primary interface between the company and external semiconductor vendors (OSATs, foundries etc.) • Lead cross-functional teams in operations, engineering, and quality assurance to meet production targets and KPIs. • Collaborate with Supply Chain and Planning to develop and execute efficient production schedules based on customer demand and inventory goals. • Develop, manage, and execute qualification activities, including prototyping parts, engineering samples and qualification builds. • Coordinate Supply Chain Planning, Procurement and Sales Operations to support product development and manufacturing ramp‑up. • Oversee Bill of Materials (BOM) accuracy and SKU management • Maintain and update internal systems to reflect NPI/engineering demand, assembly instructions, build requirements, and engineering sample plans. • Lead continuous improvement initiatives to advance operational modeling, automation, and cost‑reduction opportunities.

• Define and implement the end-to-end DFT architecture for complex SoCs, including Hierarchical DFT, Scan compression, Boundary Scan and MBIST. • Develop strategies for In-System Test (IST) and power-on self-test (POST) to ensure chip health in remote edge data centers. • Oversee scan insertion, ATPG (Stuck-at, Transition, Path Delay), and Memory/Logic BIST. • Collaborate with Design, Physical Design, and Yield teams to ensure high test coverage while minimizing area overhead and power impact as well as timing analysis. • Lead the bring-up and debug phase on ATE (Automated Test Equipment) to root-cause silicon failures and optimize test time.

EnCharge AI is a leader in advanced AI hardware and software systems for edge-to-cloud computing. EnCharge’s robust and scalable next-generation in-memory computing technology provides orders-of-magnitude higher compute efficiency and density compared to today’s best-in-class solutions. The high-performance architecture is coupled with seamless software integration and will enable the immense potential of AI to be accessible in power, energy, and space constrained applications. EnCharge AI launched in 2022 and is led by veteran technologists with backgrounds in semiconductor design and AI systems. Principal DFT Engineer Job Description: Developing silicon for AI Computing isn't just about speed; it’s about balancing high-performance data processing with extreme power efficiency and reliability in remote environments. As a Principal DFT(Design for Test) Engineer, you will lead our testing strategy, ensuring the manufacturing quality, reliability, and test efficiency of complex, high-performance AI accelerators. Key Responsibilities: Architectural Leadership: Define and implement the end-to-end DFT architecture for complex SoCs, including Hierarchical DFT, Scan compression, Boundary Scan and MBIST. Edge-Specific Reliability: Develop strategies for In-System Test (IST) and power-on self-test (POST) to ensure chip health in remote edge data centers. Implementation & Flow: Oversee scan insertion, ATPG (Stuck-at, Transition, Path Delay), and Memory/Logic BIST. Cross-Functional Synergy: Collaborate with Design, Physical Design, and Yield teams to ensure high test coverage while minimizing area overhead and power impact as well as timing analysis. Post-Silicon Validation: Lead the bring-up and debug phase on ATE (Automated Test Equipment) to root-cause silicon failures and optimize test time. Technical Requirements: Experience: 10+ years in DFT, with at least 2 years in a leadership or principal role. Tools: Mastery of industry-standard tools (e.g., Synopsys TestMAX, Siemens/Mentor Tessent, or Cadence Genus/Modus). Memory & Logic Test: Deep expertise in MBIST (Memory Built-In Self-Test) with repair capabilities, SCAN, IJTAG (IEEE 1687) and boundary scan (IEEE 1149.1/6). Advanced Nodes: Proven track record with FinFET nodes (7nm, 5nm, or below). Low Power: Experience managing DFT in multi-voltage/power-gated designs—crucial for edge efficiency. The salary range for this position is $180,000 to $220,000 per year. Actual compensation offered will be determined based by factors as job-related knowledge, skills and experience.

• Collaborate with internal Architecture, Analog and Digital Design Engineering Teams to gather information for technical documents • Writing design specifications, user manuals, and datasheets for AI Hardware • Reviewing and revising architecture specifications, conference papers, integration guides • Produce Government reports, Integration Guides, SDK User Manuals • Translates complex ASIC or VLSI concepts into clear and concise documentation for engineers and customers

EnCharge AI is a leader in advanced AI hardware and software systems for edge-to-cloud computing. EnCharge’s robust and scalable next-generation in-memory computing technology provides orders-of-magnitude higher compute efficiency and density compared to today’s best-in-class solutions. The high-performance architecture is coupled with seamless software integration and will enable the immense potential of AI to be accessible in power, energy, and space constrained applications. EnCharge AI launched in 2022 and is led by veteran technologists with backgrounds in semiconductor design and AI systems. About the Position: Hardware Technical Writer The Hardware Technical Writer will report to the Chief Operating Officer and is a Remote Virtual position. Responsibilities: - Collaborate with internal Architecture, Analog and Digital Design Engineering Teams to gather information for technical documents - Writing design specifications, user manuals, and datasheets for AI Hardware - Reviewing and revising architecture specifications, conference papers, integration guides - Produce Government reports, Integration Guides, SDK User Manuals - Translates complex ASIC or VLSI concepts into clear and concise documentation for engineers and customers Qualifications: - 5+ years experience in Technical Writing - Experience with writing technical design specifications, user manuals, and datasheets - Experience in collaborating with Engineering teams to gather technical information - Experience in Technical Writing for ASIC or VLSI teams - Work experience in Technical Writing for Artificial Intelligence companies is a plus - B.S. in Electrical Engineering or similar field - Clear communication with engineers to ensure accuracy - Experience in tools such as Markdown, LaTeX, Microsoft Word This is a 1099 contractor role. The pay range for this position is $50 to $55 USD per hour if located in US. Actual compensation offered will be determined based by factors as job-related knowledge, skills and experience.

EnCharge AI is a leader in advanced AI hardware and software systems for edge-to-cloud computing. EnCharge’s robust and scalable next-generation in-memory computing technology provides orders-of-magnitude higher compute efficiency and density compared to today’s best-in-class solutions. The high-performance architecture is coupled with seamless software integration and will enable the immense potential of AI to be accessible in power, energy, and space constrained applications. EnCharge AI launched in 2022 and is led by veteran technologists with backgrounds in semiconductor design and AI systems. About the Role We are seeking a highly experienced Senior Physical Design Engineer with a strong background in chip-level implementation and EDA tools. The ideal candidate will have deep expertise in physical design, timing closure, and low-power design. Qualifications