Role Description - Support Windows Server environments and virtual machines - Perform health checks and basic troubleshooting - Assist in Linux system support - Monitor infrastructure alerts - Support alert tuning and escalation handling - Deploy patches and applications using SCCM - Monitor client health and remediate issues - Support software distribution and compliance - Manage device enrolment and policies via Microsoft Intune - Support endpoint compliance and security baselines - Support Azure resources (VMs, storage, networking basics) - Monitor Azure alerts and basic troubleshooting - Assist in identity and access management (Entra ID) Company Description At Zensar, we’re “experience-led everything”. We are committed to conceptualizing, designing, engineering, marketing, and managing digital solutions and experiences for over 130 leading enterprises. We are a company driven by a bold purpose: Together, we shape experiences for better futures. Whether for our clients, our people, or the world around us, this belief powers everything we do. At the heart of our culture is ONE with Client - a set of four core values that reflect who we are and how we work: One Zensar, Nurturing, Empowering, and Client Focus. Part of the $4.8 billion RPG Group, we’re a community of 10,000+ innovators across 30+ global locations, including Milpitas, Seattle, Princeton, Cape Town, London, Zurich, Singapore, and Mexico City. We believe the best work happens when individuality is celebrated, growth is encouraged, and well-being is prioritized. We are an equal employment opportunity (EEO) and affirmative action employer, committed to creating an inclusive workplace. All qualified applicants will be considered without regard to race, creed, color, ancestry, religion, sex, national origin, citizenship, age, sexual orientation, gender identity, disability, marital status, family medical leave status, or protected veteran status.

Role Description We are seeking a highly experienced Lead ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC designs. This role requires deep technical ownership across: - DFT architecture - Scan insertion - ATPG - MBIST/LBIST - JTAG - Boundary scan - Post-silicon validation The ideal candidate will have strong hands-on expertise in: - DFT fundamentals - Fault models - Test coverage - Diagnosis and debug Additionally, the candidate should have the ability to evaluate and adopt emerging DFT methodologies and architecture schemes to improve robustness, quality, and yield. Qualifications - Strong hands-on experience in ASIC DFT with end-to-end ownership. - Solid understanding of DFT fundamentals, fault models, test techniques, and test coverage concepts. - Deep expertise in scan architecture, ATPG, MBIST, LBIST, JTAG, boundary scan, and silicon debug. - Hands-on experience with Synopsys, Cadence, and Siemens/Mentor EDA tools. - Proven experience in scan insertion, ATPG setup, simulation, debug, and DRC analysis. - Experience with MBIST implementation and verification; SMS experience preferred. - Experience with scan architecture and scan chain stitching; Tessent/SSN experience preferred. - Strong understanding of PLLs, RTL design, synthesis flows, logical equivalence checking (LEC), and physical design implementation. - Proven post-silicon debug and silicon bring-up experience. - Exposure to large SoC designs, hierarchical DFT flows, and multi-domain integration challenges. - Strong communication skills and the ability to work independently with minimal ramp-up. Company Description

Role Description Develops embedded software (firmware), unit/integration tests, firmware requirements, and firmware verification tests. Responsible for analyzing, designing, programming, debugging, and modification of an embedded software code base of a class III medical device. May interface with cross-functional teams to define system requirements and/or necessary modifications. Responsible for developing, applying, and maintaining quality standards in all work. Key Responsibilities - Designs, develops, debugs, modifies, tests embedded software code in C/C++ and Python. - Documents software development and/or test development by writing documents, reports, memos, change requests. Methods used are determined by approved procedures and standards. - Tracks software development effort by creating and maintaining records in the approved tracking management tool. - Analyzes, evaluates, verifies requirements, software, and systems by using software engineering practices. Quality Systems Duties and Responsibilities - Build Quality into all aspects of their work by maintaining compliance to all quality requirements. Qualifications - 5 - 13 Years with BS, 7 - 11 Years with MS, 4 - 8 Years with PhD - C / C++ experience - Experience in a regulated industry (medical device, aerospace, automotive, etc.) - Technical leadership and communication skills

Role Description We are sharing a specialised part-time consulting opportunity for US-based ASIC and SoC engineers with hands-on experience in RTL design, functional verification, hardware debugging, IP integration, timing closure, or production silicon development. This role supports an advanced AI initiative focused on improving how models understand and solve real-world semiconductor engineering problems. Selected engineers will: - Create realistic chip design and verification tasks. - Develop complete reference solutions using SystemVerilog or Verilog. - Evaluate model-generated responses. - Apply practical engineering judgment gained through design, debugging, verification, and tapeout workflows. Qualifications - Hands-on experience in ASIC or SoC design, functional verification, formal verification, or related semiconductor engineering. - Strong fluency in SystemVerilog, Verilog, or both. - Experience with production silicon, tapeout, IP development, chip integration, or subsystem verification. - Solid knowledge of interface protocols, handshaking, backpressure, multiple clock domains, and multi-module dataflow. - Experience working independently on complex design or verification problems. - Strong written communication and the ability to explain hardware engineering decisions clearly. - Reliable availability for approximately 20–40 hours per week. Requirements - A degree in electrical engineering, computer engineering, electronics engineering, computer science, or a related technical field is highly relevant. - Graduate students, recent graduates, and experienced industry professionals may all be considered. - Advanced academic or professional work in digital design, semiconductor systems, computer architecture, or verification is valuable. - Equivalent hands-on engineering experience may also be considered. Benefits - Apply practical semiconductor engineering expertise to advanced AI development. - Create realistic tasks grounded in actual chip design and verification work. - Evaluate how AI systems approach complex RTL, debugging, and hardware-reasoning problems. - Collaborate with engineers across multiple ASIC and SoC specialisations. - Work remotely with a flexible part-time commitment and competitive hourly compensation. Contract Details - Part-time W-2 contingent employment arrangement. - Fully remote role available to candidates based in the United States. - Expected commitment of approximately 20–40 hours per week depending on availability. - Candidates should have confirmed availability without scheduling conflicts. - Competitive rates between $65–$95 per hour depending on expertise and project scope. - Work may include onboarding, technical calibration, task development, model evaluation, and peer review. - Project scope, workload, and duration may be adjusted according to programme requirements and performance.