• Develops and maintains the embedded software for optical transceivers • Writing, debugging, and testing firmware for optical transceivers • Collaborating with hardware engineers to ensure the firmware works seamlessly with the transceiver's hardware • Thoroughly testing firmware to ensure it meets performance and reliability requirements • Optimizing firmware for speed, efficiency, and power consumption • Maintaining detailed documentation of firmware code and functionality

Role Description Join our high-impact Systems & Optics (SaO) team within Cisco’s Common Hardware Group (CHG), providing essential support across key verticals including SP Routing, Enterprise Routing, and Switching. Our team is a foundational partner across CHG—driving innovation, advancing design reliability, and enabling scalable hardware solutions that power Cisco’s most critical products. Cisco Hardware Engineers develop and work with Next Generation Technology to build Cisco Hardware products keeping in mind the user experience and in accordance with IEEE standards, and industry best practices. Your Impact: - Help shape next-generation package, board, and system technologies by driving advanced simulation, experimental validation, and cross-functional optimization. - Work closely with Silicon Design, Supply Chain, and Electrical Design teams. - Contribute to reliability, performance, and manufacturability across programs. - Support long-term technology roadmaps and industry leadership. - Develop and apply novel simulation and experimental methods to enable and optimize advanced hardware technologies. - Design and execute DOEs/test vehicles and computational analyses to establish design guidelines and optimize material, geometry, and architecture. - Evaluate tradeoffs across performance, reliability, and manufacturability using modeling and analysis. - Collaborate with academia and industry partners; contribute to standards bodies, conferences, IP development, and peer-reviewed publications. Qualifications - MS or PhD in Mechanical Engineering, Civil Engineering, Solid Mechanics, or Materials Science. - 5+ years of experience in numerical analysis (e.g., FEA, CFD, coupled field analysis) and advanced packaging technology development. - Strong background in mechanical design, reliability, and simulation of complex packaging structures. - Deep understanding of component- and board-level failure modes (e.g., warpage, CTE mismatch, delamination, fatigue). - Proficiency in advanced simulation tools such as ANSYS Mechanical, Multiphysics, and Flotherm. - Demonstrated expertise in reliability testing, lifetime prediction methodologies, and characterization of real-world use conditions. Requirements - Experience with Systems Integration, 2.5D/3D advanced packaging, heterogeneous integration, and emerging microelectronics technologies. - Knowledge of JEDEC or IPC standards related to reliability and thermal/mechanical testing. - Strong cross-functional collaboration skills with experience working closely with design, manufacturing, and research teams. Benefits - Medical, dental and vision insurance. - 401(k) plan with a Cisco matching contribution. - Paid parental leave. - Short and long-term disability coverage. - Basic life insurance. - 10 paid holidays per full calendar year, plus 1 floating holiday for non-exempt employees. - 1 paid day off for employee’s birthday, paid year-end holiday shutdown, and 4 paid days off for personal wellness. - 16 days of paid vacation time per full calendar year for non-exempt employees. - Flexible vacation time off program for exempt employees. - 80 hours of sick time off provided on hire date and each January 1st thereafter. - Optional 10 paid days per full calendar year to volunteer. - Eligibility for annual bonuses for non-sales roles. - Performance-based incentive pay for sales roles.

• Responsible for Synthesis, floorplanning, place & route, timing constraints, UPF and LEC • Partner with IP, Front-End logic design and Architecture teams for optimization • Lead design closure ensuring 100% verification compliance for GDSII handoff and tapeout • Architect data-driven EDA flows and methodologies with automated enhancements

• Support prototype board testing, hardware validation, board bring-up, debugging, failure analysis, and QA activities. • Work with hardware designers to debug board-level issues, verify hardware fixes, and support ECO changes during EVT/DVT/PVT validation. • Perform failure analysis for failed or returned boards and document findings. • Prepare engineering test reports, maintain board test records, and support mass production readiness reviews. • Manage prototype board tracking and shipping logistics. • Work with cross-functional teams and contract manufacturers on issue investigation, quality improvement, and production support.