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K2 Space Corporation logo
K2 Space Corporation

Building high powered satellites for a mass abundant future.

ASIC Synthesis and Timing Engineer

EngineerEngineerFull TimeRemoteMid LevelTeam 11-50Since 2022H1B No SponsorCompany SiteLinkedIn

Location

United States

Posted

43 days ago

Salary

$130K - $200K / year

Seniority

Mid Level

Bachelor Degree2 yrs expEnglish

Job Description

ASIC Synthesis and Timing Engineer

K2 Space Corporation

• Work on the RTL-to-Synthesis flow: Do synthesis at block and top level, Work with physical design team to integrate the floorplan information for physical synthesis. • Develop and maintain design methodologies, scripts, and automation to optimize performance, power, and area (PPA). • Collaborate with front-end engineers to assure timing closure, and efficient design iteration. • Drive timing closure across multiple voltage and process corners, including sign-off with foundry-qualified tools. • Own Lint, CDC and UPF checks and drive collaboration to close out issues. • Develop an end to end formal verification methodology without any gap to deliver on full confidence functionality between the RTL and the post layout netlist. • Manage and technically guide external physical design partners and service vendors, ensuring alignment on milestones, deliverables, and quality standards. • Work with EDA vendors to debug and optimize tool flows, and evaluate new methodologies. • Support chip bring-up and debug through close collaboration with post-silicon and test teams. • Support your product through production and spaceflight.

Job Requirements

  • B.S. or M.S. in Electrical Engineering, Computer Engineering, or related field.
  • 2+ years of experience in ASIC design for high-performance blocks of SoCs.
  • Proven end-to-end expertise in RTL-to-GDSII flows using industry tools (Synopsys, Cadence, or Siemens).
  • Strong hands-on experience with Synthesis, constraints development
  • Deep understanding of physical design constraints for multi-clock, multi-voltage, and hierarchical SoCs.
  • Experience with advanced FinFET process nodes.
  • Prior experience in design convergence with offshore/outsourced PD teams or vendors.
  • Able to resolve formal verification issues.
  • Able to analyze and fix VCLP issues regarding UPF.
  • Experience with Logic equivalence check debug, Functional ECO development and implementation with minimal database disruption, Low power checker to validate UPF;
  • Familiarity with DFT integration, STA sign-off with functional ECO implementation.
  • Excellent communication, leadership, and cross-functional collaboration skills.

Benefits

  • Comprehensive benefits package including paid time off
  • Medical/dental/vision coverage
  • Life insurance
  • Paid parental leave
  • Many other perks

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