K2 is building the largest and highest-power satellites ever flown, unlocking performance levels previously out of reach across every orbit. Backed by $450M from leading investors including Altimeter Capital, Redpoint Ventures, T. Rowe Price, Lightspeed Venture Partners, Alpine Space Ventures, and others – with an additional $500M in signed contracts across commercial and US government customers – we’re mass-producing the highest-power satellite platforms ever built for missions from LEO to deep space. The rise of heavy-lift launch vehicles is shifting the industry from an era of mass constraint to one of mass abundance, and we believe this new era demands a fundamentally different class of spacecraft. Engineered to survive the harshest radiation environments and to fully capitalize on today’s and tomorrow’s massive rockets, K2 satellites deliver unmatched capability at constellation scale and across multiple orbits. With multiple launches planned through 2026 and 2027, we're Building Bigger to develop the solar system and become a Kardashev Type II (K2) civilization. If you are a motivated individual who thrives in a fast-paced environment and you're excited about contributing to the success of a groundbreaking Series C space startup, we’d love for you to apply. The Role We are seeking a highly skilled Senior Mixed-Signal IC Design Engineer with strong expertise in high-speed data converter (ADC/DAC) and Phase-Locked Loop (PLL) design, particularly in advanced FinFET technology nodes. You will be part of a collaborative design team developing state-of-the-art mixed-signal SoCs to be hosted on some of the largest, most powerful, rapidly designed and rapidly manufactured satellites ever deployed in space. In your first 6 months, you will architect, develop, and implement new SoC sub-systems for satellite communications and beyond. In your first two years, you will have flown your sub-system in space and developed cutting-edge mixed-signal SoCs. Responsibilities - Design and develop high-performance, high-speed ADC and DAC architectures. - Architect and implement low-jitter, low-power integer-N and fractional-N PLLs, frequency synthesizers and clocking systems. - Engage with cross-functional analog, digital, DV, firmware, SoC architecture, technology, packaging, silicon validation, production test, and manufacturing teams to implement circuits and sub-systems. - Drive full lifecycle design including specification, modeling (Verilog-A/AMS), schematic design, simulation, post-layout verification, and silicon validation. - Perform design optimization for power, area, and performance in advanced FinFET nodes. - Develop and maintain design documentation and support post-silicon bring-up and characterization. - Support your product through production and spaceflight. - Act as technical leader and subject-matter expert helping to teach, grow, and mentor others in the team. Qualifications - M.S. or Ph.D. in Electrical Engineering with a strong focus in analog/mixed-signal IC design. - 5+ years of relevant industry experience in mixed-signal circuit design. - Proven hands-on experience in high-speed ADC/DAC designs with deep understanding of architectures, performance metrics, and design trade-offs. - Strong knowledge of PLL design principles, including charge pump, VCO, loop filter, multi-modulus divider, sigma delta modulator, and jitter analysis. - Solid understanding of FinFET CMOS process characteristics and layout parasitic considerations. - Proficient in EDA tools such as Cadence Virtuoso, Spectre, behavioral modeling (Verilog-A, Verilog-AMS, MATLAB), and similar tools. - Strong debugging, problem-solving, and communication skills. Nice to Have - Familiarity with various RF transceiver architectures and their trade-offs, systems specifications, and ability to translate system requirements into circuit requirements. - Tape-out experience in advanced FinFET nodes. - Familiarity with digital calibration techniques and DSP-assisted mixed-signal systems. - Solid understanding of and experience with building block circuits such as bandgaps, bias generators, TIAs, op-amps, filters, and LDOs. - Exposure to EM/Reliability/ESD design best practices. - Experience working in cross-functional, geographically distributed teams. Compensation and Benefits: - Base salary range for this role is $170,000 - $250,000 + equity in the company - Salary will be based on several factors including, but not limited to: knowledge and skills, education, and experience level - Comprehensive benefits package including unlimited paid time off, medical/dental/vision coverage, life insurance, paid parental leave, and many other perks If you don’t meet 100% of the preferred skills and experience, we encourage you to still apply! Building a spacecraft unlike any other requires a team unlike any other and non-traditional career twists and turns are encouraged! If you need a reasonable accommodation as part of your application for employment or interviews with us, please let us know. Export Compliance As defined in the ITAR, “U.S. Persons” include U.S. citizens, lawful permanent residents (i.e., Green Card holders), and certain protected individuals (e.g., refugees/asylees, American Samoans). Please consult with a knowledgeable advisor if you are unsure whether you are a “U.S. Person.” The person hired for this role will have access to information and items controlled by U.S. export control regulations, including the export control regulations outlined in the International Traffic in Arms Regulation (ITAR). The person hired for this role must therefore either be a “U.S. person” as defined by 22 C.F.R. § 120.15 or otherwise eligible for a federally issued export control license. Equal Opportunity K2 Space is an Equal Opportunity Employer; employment with K2 Space is governed on the basis of merit, competence and qualifications and will not be influenced in any manner by race, color, religion, gender, national origin/ethnicity, veteran status, disability status, age, sexual orientation, gender identity, marital status, mental or physical disability or any other legally protected status.

K2 is building the largest and highest-power satellites ever flown, unlocking performance levels previously out of reach across every orbit. Backed by $450M from leading investors including Altimeter Capital, Redpoint Ventures, T. Rowe Price, Lightspeed Venture Partners, Alpine Space Ventures, and others – with an additional $500M in signed contracts across commercial and US government customers – we’re mass-producing the highest-power satellite platforms ever built for missions from LEO to deep space. The rise of heavy-lift launch vehicles is shifting the industry from an era of mass constraint to one of mass abundance, and we believe this new era demands a fundamentally different class of spacecraft. Engineered to survive the harshest radiation environments and to fully capitalize on today’s and tomorrow’s massive rockets, K2 satellites deliver unmatched capability at constellation scale and across multiple orbits. With multiple launches planned through 2026 and 2027, we're Building Bigger to develop the solar system and become a Kardashev Type II (K2) civilization. If you are a motivated individual who thrives in a fast-paced environment and you're excited about contributing to the success of a groundbreaking Series C space startup, we’d love for you to apply. The Role We are seeking a highly skilled Principal Digital ASIC Design Engineer to lead the design and implementation of digital subsystems for advanced wireless SoCs. You will be part of a collaborative design team developing state-of-the-art mixed-signal SoCs to be hosted on some of the largest, most powerful, rapidly designed and rapidly manufactured satellites ever deployed in space. In your first 6 months, you will architect, develop, and implement new SoC sub-systems for satellite communications and beyond. In your first two years, you will have flown your sub-system in space and developed cutting-edge mixed-signal SoCs. Responsibilities - Own the architecture, microarchitecture, RTL implementation, and integration of key digital blocks in wireless SoCs. - Collaborate with system architects to translate high-level DSP algorithms into efficient hardware implementations. - Drive end-to-end development of DSP systems (e.g., filters, beamformers, FFT/IFFT engines). - Convert chip specifications into RTL using internal IPs and external IPs. - Design and develop RTL for interfaces, power management, clocking, reset, test & debug. - Partner with analog/mixed-signal teams to define digital-analog interfaces, calibration engines, and control logic. - Optimize designs for power, performance, and area (PPA) and support timing closure through synthesis and backend collaboration. - Lead or contribute to verification planning and validation of complex digital subsystems. - Participate in chip bring-up and lab validation of complex digital subsystems. - Support your product through production and spaceflight. - Act as a technical leader and subject-matter expert, helping to teach, grow, and mentor others in the team. Qualifications - B.S. or M.S. in Electrical Engineering, Computer Engineering, or related field. - 10+ years of relevant industry experience in digital ASIC design, with significant ownership of complex subsystems. - Proficiency in RTL design (SystemVerilog or Verilog), synthesis, and linting tools. - Experience in micro-architecture definition from architecture guideline and model analysis. - Experience in closing full-chip and subsystem timing working with synthesis and static analysis teams. - Experience with DFT tools for scan and BIST insertion. - Solid understanding of SoC design flows including clock/power domain crossing, timing constraints, and formal verification. - Experience developing and integrating DSP blocks for wireless communication (e.g. OFDM, MIMO, channel estimation, DFE, etc.). - Strong experience with EDA tools for design, synthesis, static timing analysis, and power analysis (e.g. Synopsys, Cadence, Siemens tools). - Strong debugging, problem-solving, and communication skills. Nice to Have - Prior experience in wireless SoC development (e.g. cellular, Wi-Fi, satellite, or mmWave systems) and successful tapeouts in advanced design nodes. - Design experience in datapath, flow control, arbitration, FIFO, DMA, IOMMU, SoC bus architecture, ARM’s AXI/AHB bus architecture & protocols, serial interfaces such as SPI, I3C, UART. - Familiarity with DSP algorithm modeling (MATLAB, Python, or C++) and converting models into RTL. - Experience working with FEC, baseband PHYs, or digital beamforming architectures. - Knowledge of digital calibration and control of RF/mixed-signal front ends. - Exposure to hardware-software co-design and embedded process integration. - Experience working in cross-functional, geographically distributed teams. Compensation and Benefits: - Base salary range for this role is $190,000 – $285,000 + equity in the company - Salary will be based on several factors including, but not limited to: knowledge and skills, education, and experience level - Comprehensive benefits package including paid time off, medical/dental/vision/ coverage, life insurance, paid parental leave, and many other perks If you don’t meet 100% of the preferred skills and experience, we encourage you to still apply! Building a spacecraft unlike any other requires a team unlike any other and non-traditional career twists and turns are encouraged! If you need a reasonable accommodation as part of your application for employment or interviews with us, please let us know. Export Compliance As defined in the ITAR, “U.S. Persons” include U.S. citizens, lawful permanent residents (i.e., Green Card holders), and certain protected individuals (e.g., refugees/asylees, American Samoans). Please consult with a knowledgeable advisor if you are unsure whether you are a “U.S. Person.” The person hired for this role will have access to information and items controlled by U.S. export control regulations, including the export control regulations outlined in the International Traffic in Arms Regulation (ITAR). The person hired for this role must therefore either be a “U.S. person” as defined by 22 C.F.R. § 120.15 or otherwise eligible for a federally issued export control license. Equal Opportunity K2 Space is an Equal Opportunity Employer; employment with K2 Space is governed on the basis of merit, competence and qualifications and will not be influenced in any manner by race, color, religion, gender, national origin/ethnicity, veteran status, disability status, age, sexual orientation, gender identity, marital status, mental or physical disability or any other legally protected status.

Position: FPGA Design Engineer Job Description: Location: Mountain View, CA (Remote) What will you do: - Strong expertise on Arteris/ NOC Design Toolset - At-least 5+ years of experience in Verilog Design - AMBA AXI bus along-with ARM or C based processor - Ensure customer satisfaction. - Reporting to customers on daily or weekly progress effectively What we are looking for: - Strong expertise along-with complex SoC/IP debug is must - At-least 5+ years of experience in System Verilog HVL and C/C++. - AMBA AXI bus along-with ARM or C based processor - Bi-frost/Processor based C and SV/UVM mix Verification. - Experience in complete verification cycle which includes development of test plan, - BFM/Driver/Monitor/Scoreboard component development and integration in test bench, - stress/corner testing, failure debug, gate level simulations, assertions, and coverage closure. - Make/Perl/Python What’s In It for You: At Arrow, we recognize that financial rewards and great benefits are important aspects of an ideal job. That’s why we offer competitive financial compensation, including various compensation plans and a solid benefits package. • Medical, Dental, Vision Insurance • 401k, With Matching Contributions • Short-Term/Long-Term Disability Insurance • Health Savings Account (HSA)/Health Reimbursement Account (HRA) Options • Paid Time Off (including sick, holiday, vacation, etc.) • Tuition Reimbursement • Growth Opportunities • And more! About eInfochips: eInfochips, an Arrow company (Fortune #154), is a leading global provider of product engineering and semiconductor design services. A rich history of over two decades, with over 500+ products developed and 40M deployments in 140 countries, eInfochips continues to fuel technological innovations in multiple verticals. eInfochips has strategic technology partnerships with Qualcomm, NVIDIA, NXP, Analog Devices, Texas Instruments, Amazon, Microsoft and Google to name a few. Along with Arrow’s $38B in revenues, 22,000 employees, and 345 locations serving over 80 countries, eInfochips is primed to accelerate connected products innovation for 150,000+ global clients. eInfochips acts as a catalyst to Arrow’s Sensor-to-Sunset initiative and offers complete edgeto-cloud capabilities for its clients. Please visit www.einfochips.com for our portfolio of product engineering services across various industries s verticals. EEO Statement: Arrow is an equal opportunity employer. All applicants will be considered for employment without attention to race, color, religion, gender, age, sexual orientation, gender identity, national origin, veteran or disability status. (Arrow EEO/AAP policy) Annual Hiring Range/Hourly Rate: $95,900.00 - $203,500.00 Actual compensation offer to candidate may vary from posted hiring range based upon geographic location, work experience, education, and/or skill level. The pay ratio between base pay and target incentive (if applicable) will be finalized at offer. Location: US-CA-San Jose, California (eInfochips) Remote work employees may be required to be present at the closest designated Arrow office for work-related purposes, at the Company’s request and sole discretion. Time Type: Full time Job Category: Engineering Services EEO Statement: Arrow is an equal opportunity employer. All applicants will be considered for employment without attention to race, color, religion, gender, age, sexual orientation, gender identity, national origin, veteran or disability status. (Arrow EEO/AAP policy) We anticipate this requisition will be open for a minimum of five days, though it may be open for a longer period of time. We encourage your prompt application. In any materials you submit, you may redact or remove age-identifying information such as age, date of birth, or dates of school attendance or graduation. You will not be penalized for redacting or removing this information.

Position: FPGA Design Engineer Job Description: Location: Mountain View, CA (Remote) What will you do: - Strong expertise on Arteris/ NOC Design Toolset - At-least 5+ years of experience in Verilog Design - AMBA AXI bus along-with ARM or C based processor - Ensure customer satisfaction. - Reporting to customers on daily or weekly progress effectively What we are looking for: - Strong expertise along-with complex SoC/IP debug is must - At-least 5+ years of experience in System Verilog HVL and C/C++. - AMBA AXI bus along-with ARM or C based processor - Bi-frost/Processor based C and SV/UVM mix Verification. - Experience in complete verification cycle which includes development of test plan, - BFM/Driver/Monitor/Scoreboard component development and integration in test bench, - stress/corner testing, failure debug, gate level simulations, assertions, and coverage closure. - Make/Perl/Python What’s In It for You: At Arrow, we recognize that financial rewards and great benefits are important aspects of an ideal job. That’s why we offer competitive financial compensation, including various compensation plans and a solid benefits package. • Medical, Dental, Vision Insurance • 401k, With Matching Contributions • Short-Term/Long-Term Disability Insurance • Health Savings Account (HSA)/Health Reimbursement Account (HRA) Options • Paid Time Off (including sick, holiday, vacation, etc.) • Tuition Reimbursement • Growth Opportunities • And more! About eInfochips: eInfochips, an Arrow company (Fortune #154), is a leading global provider of product engineering and semiconductor design services. A rich history of over two decades, with over 500+ products developed and 40M deployments in 140 countries, eInfochips continues to fuel technological innovations in multiple verticals. eInfochips has strategic technology partnerships with Qualcomm, NVIDIA, NXP, Analog Devices, Texas Instruments, Amazon, Microsoft and Google to name a few. Along with Arrow’s $38B in revenues, 22,000 employees, and 345 locations serving over 80 countries, eInfochips is primed to accelerate connected products innovation for 150,000+ global clients. eInfochips acts as a catalyst to Arrow’s Sensor-to-Sunset initiative and offers complete edgeto-cloud capabilities for its clients. Please visit www.einfochips.com for our portfolio of product engineering services across various industries s verticals. EEO Statement: Arrow is an equal opportunity employer. All applicants will be considered for employment without attention to race, color, religion, gender, age, sexual orientation, gender identity, national origin, veteran or disability status. (Arrow EEO/AAP policy) Annual Hiring Range/Hourly Rate: $95,900.00 - $203,500.00 Actual compensation offer to candidate may vary from posted hiring range based upon geographic location, work experience, education, and/or skill level. The pay ratio between base pay and target incentive (if applicable) will be finalized at offer. Location: US-CA-San Jose, California (eInfochips) Remote work employees may be required to be present at the closest designated Arrow office for work-related purposes, at the Company’s request and sole discretion. Time Type: Full time Job Category: Engineering Services EEO Statement: Arrow is an equal opportunity employer. All applicants will be considered for employment without attention to race, color, religion, gender, age, sexual orientation, gender identity, national origin, veteran or disability status. (Arrow EEO/AAP policy) We anticipate this requisition will be open for a minimum of five days, though it may be open for a longer period of time. We encourage your prompt application. In any materials you submit, you may redact or remove age-identifying information such as age, date of birth, or dates of school attendance or graduation. You will not be penalized for redacting or removing this information.