K2 Space

Role Description We are seeking an ASIC Design Verification Engineer whose role will be to verify the functionality, performance, and robustness of our custom silicon designs. You will help define the verification approach, contribute to methodology, and work closely with architecture, RTL design, DFT, firmware, physical design, and silicon validation engineers. This is a hands-on role with high ownership, deep technical engagement, and the opportunity to shape first-generation silicon. Responsibilities - Develop and execute verification plans for block-level, subsystem-level, and full-chip environments. - Build SystemVerilog/UVM test benches, including agents, monitors, scoreboards, checkers, and coverage models. - Write SystemVerilog Assertions (SVA) and integrate formal verification where appropriate. - Drive constrained-random and directed testing strategies to validate functionality, corner cases, and stress scenarios. - Run simulations, triage failures, drive root-cause analysis, and collaborate with RTL designers to resolve issues. - Implement and maintain functional coverage, code coverage, assertion coverage, and ensure coverage closure for sign-off. - Manage regression testing, simulation farms, and CI pipelines to ensure high test throughput and fast debug iterations. - Participate in design reviews and microarchitecture discussions. Qualifications - B.S. or M.S. in Electrical Engineering, Computer Engineering, or related field. - 3+ years of experience in ASIC/SoC verification. - Solid understanding of SystemVerilog, digital logic, and hardware verification flows. - Proficiency with a simulation (VCS, Xcelium, Questa), waveform debug (Verdi, SimVision) and coverage tool. - Experience with test planning, testbench development, constrained-random testing, and coverage analysis. - Familiarity with a scripting language (ex: Python, Perl, TCL) and revision control system (ex: Git). Nice to Have - Experience with UVM-based testbench development, functional coverage, SystemVerilog assertions, and regression management. - Familiarity with developing and integrating reference models. - Understanding of RTL design flows and some industry standard interfaces (ex: APB/AHB/AXI). - Experience working in cross-functional, geographically distributed teams. - Experience in space, telecom, or RF/digital mixed systems is a plus. Compensation and Benefits - Base salary range for this role is $130,000 – $200,000 + equity in the company. - Salary will be based on several factors including, but not limited to: knowledge and skills, education, and experience level. - Comprehensive benefits package including paid time off, medical/dental/vision coverage, life insurance, paid parental leave, and many other perks.

Role Description We are seeking a Senior ASIC Design Verification Engineer whose role will be to verify the functionality, performance, and robustness of our custom silicon designs. You will help define the verification approach, contribute to methodology, and work closely with architecture, RTL design, DFT, firmware, physical design, and silicon validation engineers. This is a hands-on role with high ownership, deep technical engagement, and the opportunity to shape first-generation silicon. Responsibilities - Develop and execute verification plans for block-level, subsystem-level, and full-chip environments. - Build SystemVerilog/UVM test benches, including agents, monitors, scoreboards, checkers, and coverage models. - Write SystemVerilog Assertions (SVA) and integrate formal verification where appropriate. - Drive constrained-random and directed testing strategies to validate functionality, corner cases, and stress scenarios. - Run simulations, triage failures, drive root-cause analysis, and collaborate with RTL designers to resolve issues. - Implement and maintain functional coverage, code coverage, assertion coverage, and ensure coverage closure for sign-off. - Manage regression testing, simulation farms, and CI pipelines to ensure high test throughput and fast debug iterations. - Participate in design reviews, microarchitecture discussions, and influence design-for-verification (DFV) best practices. - Work closely with architecture, RTL design, DFT, firmware, physical design, and silicon validation engineers to ensure end-to-end coverage and test. - Support silicon bring-up and post-silicon validation through test reuse, diagnostics, and debug analysis. - Participate in ASIC team interviews. - Contribute to advancement of DV methodologies and improvements. - Engage external IP providers and verification partners when needed. Qualifications - B.S. or M.S. in Electrical Engineering, Computer Engineering, or related field. - 5+ years of experience in ASIC/SoC verification. - Solid understanding of SystemVerilog, digital logic, RTL design, and hardware verification flows. - Proficiency with a simulation (VCS, Xcelium, Questa), waveform debug (Verdi, SimVision), coverage tool, and scripting languages (ex: Python, Perl, TCL). - Experience with test planning, UVM-based testbench development, constrained-random testing, functional coverage, and SystemVerilog assertions. - Experience with regression management, coverage analysis, revision control (Git), and CI/CD automation. - Understanding of several industry-standard interfaces (ex: APB/AHB/AXI). - Familiarity with embedded processor-based designs and firmware/bare metal coding (ex: C, C++). Nice to Have - Experience with developing and integrating reference models. - Understanding of low power verification. - Familiarity with gate-level simulation and analog behavioral models. - Involvement in post-silicon validation planning and execution. - Experience working in cross-functional, geographically distributed teams. - Experience in space, telecom, or RF/digital mixed systems is a plus. Benefits - Base salary range for this role is $170,000 – $250,000 + equity in the company. - Salary will be based on several factors including, but not limited to: knowledge and skills, education, and experience level. - Comprehensive benefits package including paid time off, medical/dental/vision coverage, life insurance, paid parental leave, and many other perks.

K2 is building the largest and highest-power satellites ever flown, unlocking performance levels previously out of reach across every orbit. Backed by $450M from leading investors including Altimeter Capital, Redpoint Ventures, T. Rowe Price, Lightspeed Venture Partners, Alpine Space Ventures, and others – with an additional $500M in signed contracts across commercial and US government customers – we’re mass-producing the highest-power satellite platforms ever built for missions from LEO to deep space. The rise of heavy-lift launch vehicles is shifting the industry from an era of mass constraint to one of mass abundance, and we believe this new era demands a fundamentally different class of spacecraft. Engineered to survive the harshest radiation environments and to fully capitalize on today’s and tomorrow’s massive rockets, K2 satellites deliver unmatched capability at constellation scale and across multiple orbits. With multiple launches planned through 2026 and 2027, we're Building Bigger to develop the solar system and become a Kardashev Type II (K2) civilization. If you are a motivated individual who thrives in a fast-paced environment and you're excited about contributing to the success of a groundbreaking Series C space startup, we’d love for you to apply. The Role As a Senior GNC engineer, you will be a core driver of the overall spacecraft GNC architecture. You will execute detailed trade studies to find new and novel ways to implement the spacecraft’s orbital guidance, orbital control, and attitude and orbit estimation systems. In the first 3 months, you will support the development/improvement of the MEO navigation, taking lessons learned from the Gravitas mission and applying them to the baseline GNC stack. In the first 6 months you will support the development of new and novel navigation approaches to support future programs – specifically solving navigation for GEO, cis lunar, and interplanetary. In parallel you will support the development of the in-house trajectory design scheme and associated analysis workflow. As we learn more about our system, this will lead to updates to both the GNC stack and the K2 6-DOF simulation. The expectation is that all GNC team members commit code to the 6-DOF sim as well as owning a portion of the GNC flight software. In the first year, you will support launch and on orbit operations of the Trinity mission – the stacked launch of 3 K2 Mega spacecraft. In parallel, you will continue to support improvements, closing the loop on the design, build, test, fly lifecycle. Responsibilities - Work with other engineering leads to develop and validate a novel high level vehicle architecture - Develop novel algorithms for precise navigation in LEO, MEO, GEO, cis lunar, and interplanetary space. - Develop simulation and modeling tools to support vehicle and GNC trade studies. This includes mission design, controls analysis, and 6-DOF simulation development. - Contribute to building the GNC organization by recruiting, hiring, and mentoring other engineers Qualifications - Experience with implementing estimation algorithms on for flight software and ground software, specifically Kalman Filters, Extended Kalman Filters, and Unscented Kalman Filters - Experience performing Monte Carlo based analyses and covariance analysis - Experience with verification and validation of GNC flight software in an integrated environment, leveraging 6-DOF simulation and HITL testing. - Experience with GNC sensor sizing, selection, and system design - Experience with Python, Julia, C/C++, Rust, or Matlab for algorithm development, implementation, and simulation Nice to Have - Experience with system identification, leveraging on-orbit data - Experience with early-stage spacecraft conceptual design, i.e. “clean sheet” design work - Breadth in control algorithm development - Experience with reaction wheel, control moment gyroscope, or thruster sizing and algorithm implementation - Experience with trajectory analysis, modeling, optimization, and mission design for GEO, cislunar, interplanetary missions Compensation and Benefits: - Base salary range for this role is $160,000 - $235,000 + equity in the company - Salary will be based on several factors including, but not limited to: knowledge and skills, education, and experience level - Comprehensive benefits package including paid time off, medical/dental/vision coverage, life insurance, paid parental leave, and many other perks If you don’t meet 100% of the preferred skills and experience, we encourage you to still apply! Building a spacecraft unlike any other requires a team unlike any other and non-traditional career twists and turns are encouraged! If you need a reasonable accommodation as part of your application for employment or interviews with us, please let us know. Export Compliance As defined in the ITAR, “U.S. Persons” include U.S. citizens, lawful permanent residents (i.e., Green Card holders), and certain protected individuals (e.g., refugees/asylees, American Samoans). Please consult with a knowledgeable advisor if you are unsure whether you are a “U.S. Person.” The person hired for this role will have access to information and items controlled by U.S. export control regulations, including the export control regulations outlined in the International Traffic in Arms Regulation (ITAR). The person hired for this role must therefore either be a “U.S. person” as defined by 22 C.F.R. § 120.15 or otherwise eligible for a federally issued export control license. Equal Opportunity K2 Space is an Equal Opportunity Employer; employment with K2 Space is governed on the basis of merit, competence and qualifications and will not be influenced in any manner by race, color, religion, gender, national origin/ethnicity, veteran status, disability status, age, sexual orientation, gender identity, marital status, mental or physical disability or any other legally protected status.

K2 is building the largest and highest-power satellites ever flown, unlocking performance levels previously out of reach across every orbit. Backed by $450M from leading investors including Altimeter Capital, Redpoint Ventures, T. Rowe Price, Lightspeed Venture Partners, Alpine Space Ventures, and others – with an additional $500M in signed contracts across commercial and US government customers – we’re mass-producing the highest-power satellite platforms ever built for missions from LEO to deep space. The rise of heavy-lift launch vehicles is shifting the industry from an era of mass constraint to one of mass abundance, and we believe this new era demands a fundamentally different class of spacecraft. Engineered to survive the harshest radiation environments and to fully capitalize on today’s and tomorrow’s massive rockets, K2 satellites deliver unmatched capability at constellation scale and across multiple orbits. With multiple launches planned through 2026 and 2027, we're Building Bigger to develop the solar system and become a Kardashev Type II (K2) civilization. If you are a motivated individual who thrives in a fast-paced environment and you're excited about contributing to the success of a groundbreaking Series C space startup, we’d love for you to apply. The Role We are looking for a Principal ASIC Physical Design Engineer to lead the implementation of complex SoCs for next-generation satellite and space systems. You will own the full physical design flow—from RTL handoff to GDSII—and collaborate closely with architecture, RTL design, DFT, and packaging teams. This role also involves managing external physical design partners, driving tool and flow decisions, and ensuring first-pass silicon success in advanced FinFET technologies. You’ll be a key contributor in achieving timing closure, optimizing PPA, and supporting design integration with external partners. You will be part of a collaborative design team developing state-of-the-art mixed-signal SoCs to be hosted on some of the largest, most powerful, rapidly designed and rapidly manufactured satellites ever deployed in space. In your first 6 months, you will develop and implement new SoC sub-systems for satellite communications and beyond. In your first two years, you will have contributed to developing cutting-edge SoCs that will fly in space. Responsibilities - Own the complete RTL-to-GDSII flow: synthesis, floorplanning, place & route, clock tree synthesis (CTS), static timing analysis (STA), physical verification (DRC/LVS), and sign-off. - Develop and maintain physical design methodologies, scripts, and automation to optimize performance, power, and area (PPA). - Collaborate with front-end and verification teams to ensure clean handoffs, timing closure, and efficient design iteration. - Drive timing closure across multiple voltage and process corners, including sign-off with foundry-qualified tools. - Partner with package, SI/PI, and test teams for package-aware floorplanning and chip-to-board integration. - Manage and technically guide external physical design partners and service vendors, ensuring alignment on milestones, deliverables, and quality standards. - Work with EDA vendors to debug and optimize tool flows, and evaluate new methodologies. - Support chip bring-up and debug through close collaboration with post-silicon and test teams. - Support your product through production and spaceflight. Required Qualifications - Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field. - 10+ years of experience in ASIC physical design for high-performance SoCs. - Proven end-to-end expertise in RTL-to-GDSII flows using industry tools (Synopsys, Cadence, or Siemens). - Strong hands-on experience with timing closure, IR drop analysis, and ECO implementation. - Deep understanding of physical design constraints for multi-clock, multi-voltage, and hierarchical SoCs. - Experience with advanced FinFET process nodes. - Prior experience managing or coordinating offshore/outsourced PD teams or vendors. - Familiarity with DFT integration, STA sign-off, and power domain implementation (UPF/CPF). - Excellent communication, leadership, and cross-functional collaboration skills. - Act as technical leader and subject-matter expert helping to teach, grow, and mentor others in the team. Preferred Qualifications - Exposure to radiation-hardened or space-qualified ASICs. - Experience with chip-package co-design or advanced packaging (2.5D/3D). - Familiarity with physical design service vendor management or offshore collaboration. - Experience driving tapeouts through TSMC. - Experience with Gate-All-Around technologies. - Experience working in cross-functional, geographically distributed teams. Compensation and Benefits: - Base salary range for this role is $190,000 – $280,000 + equity in the company - Salary will be based on several factors including, but not limited to: knowledge and skills, education, and experience level - Comprehensive benefits package including paid time off, medical/dental/vision/ coverage, life insurance, paid parental leave, and many other perks If you don’t meet 100% of the preferred skills and experience, we encourage you to still apply! Building a spacecraft unlike any other requires a team unlike any other and non-traditional career twists and turns are encouraged! If you need a reasonable accommodation as part of your application for employment or interviews with us, please let us know. Export Compliance As defined in the ITAR, “U.S. Persons” include U.S. citizens, lawful permanent residents (i.e., Green Card holders), and certain protected individuals (e.g., refugees/asylees, American Samoans). Please consult with a knowledgeable advisor if you are unsure whether you are a “U.S. Person.” The person hired for this role will have access to information and items controlled by U.S. export control regulations, including the export control regulations outlined in the International Traffic in Arms Regulation (ITAR). The person hired for this role must therefore either be a “U.S. person” as defined by 22 C.F.R. § 120.15 or otherwise eligible for a federally issued export control license. Equal Opportunity K2 Space is an Equal Opportunity Employer; employment with K2 Space is governed on the basis of merit, competence and qualifications and will not be influenced in any manner by race, color, religion, gender, national origin/ethnicity, veteran status, disability status, age, sexual orientation, gender identity, marital status, mental or physical disability or any other legally protected status.

K2 is building the largest and highest-power satellites ever flown, unlocking performance levels previously out of reach across every orbit. Backed by $450M from leading investors including Altimeter Capital, Redpoint Ventures, T. Rowe Price, Lightspeed Venture Partners, Alpine Space Ventures, and others – with an additional $500M in signed contracts across commercial and US government customers – we’re mass-producing the highest-power satellite platforms ever built for missions from LEO to deep space. The rise of heavy-lift launch vehicles is shifting the industry from an era of mass constraint to one of mass abundance, and we believe this new era demands a fundamentally different class of spacecraft. Engineered to survive the harshest radiation environments and to fully capitalize on today’s and tomorrow’s massive rockets, K2 satellites deliver unmatched capability at constellation scale and across multiple orbits. With multiple launches planned through 2026 and 2027, we're Building Bigger to develop the solar system and become a Kardashev Type II (K2) civilization. If you are a motivated individual who thrives in a fast-paced environment and you're excited about contributing to the success of a groundbreaking Series C space startup, we’d love for you to apply. The Role We are seeking a Senior ASIC Physical Design Engineer to help implement advanced SoCs that power next-generation satellite and space systems. In this role, you will contribute to the full physical design flow—from synthesis to GDSII—working closely with architecture, RTL, verification, and packaging teams. You’ll be a key contributor in achieving timing closure, optimizing PPA, and supporting design integration with external partners. You will be part of a collaborative design team developing state-of-the-art mixed-signal SoCs to be hosted on some of the largest, most powerful, rapidly designed and rapidly manufactured satellites ever deployed in space. In your first 6 months, you will develop and implement new SoC sub-systems for satellite communications and beyond. In your first two years, you will have contributed to developing cutting-edge SoCs that will fly in space.  Responsibilities - Execute the complete physical design flow for complex SoC blocks and top-level integration, including synthesis, floorplanning, place & route, CTS, STA, and physical verification. - Perform timing closure and optimization across multiple corners and modes using industry-standard tools. - Collaborate with front-end, verification, and DFT teams to ensure clean handoff and predictable convergence. - Work with external physical design service providers and internal leads to review deliverables, resolve issues, and ensure schedule alignment. - Develop and maintain scripts and automation to improve flow efficiency and consistency. - Support physical sign-off activities including DRC/LVS, IR drop, EM, and power analysis. - Assist in chip-level integration, ECOs, and tapeout preparation. - Contribute to methodology development, tool evaluation, and flow documentation. - Support your product through production and spaceflight. Required Qualifications  - Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field. - 5–10 years of experience in ASIC physical design for complex SoCs. - Hands-on experience with industry-standard tools (Synopsys ICC2/Fusion Compiler, Cadence Innovus, or equivalent). - Strong understanding of timing analysis, power optimization, and physical verification flows. - Experience with hierarchical or flat SoC design methodologies. - Familiarity with FinFET technologies. - Working knowledge of DFT, UPF/CPF power intent, and ECO implementation. - Strong problem-solving skills and ability to work cross-functionally in fast-paced environments. Preferred Qualifications  - Exposure to radiation-hardened or space-qualified ASICs. - Experience with chip-package co-design or advanced packaging (2.5D/3D). - Familiarity with physical design service vendor management or offshore collaboration. - Experience with sign-off through TSMC. - Experience with Gate-All-Around technologies. - Experience working in cross-functional, geographically distributed teams. Compensation and Benefits: - Base salary range for this role is $170,000 – $250,000 + equity in the company - Salary will be based on several factors including, but not limited to: knowledge and skills, education, and experience level - Comprehensive benefits package including paid time off, medical/dental/vision/ coverage, life insurance, paid parental leave, and many other perks If you don’t meet 100% of the preferred skills and experience, we encourage you to still apply! Building a spacecraft unlike any other requires a team unlike any other and non-traditional career twists and turns are encouraged! If you need a reasonable accommodation as part of your application for employment or interviews with us, please let us know. Export Compliance As defined in the ITAR, “U.S. Persons” include U.S. citizens, lawful permanent residents (i.e., Green Card holders), and certain protected individuals (e.g., refugees/asylees, American Samoans). Please consult with a knowledgeable advisor if you are unsure whether you are a “U.S. Person.” The person hired for this role will have access to information and items controlled by U.S. export control regulations, including the export control regulations outlined in the International Traffic in Arms Regulation (ITAR). The person hired for this role must therefore either be a “U.S. person” as defined by 22 C.F.R. § 120.15 or otherwise eligible for a federally issued export control license. Equal Opportunity K2 Space is an Equal Opportunity Employer; employment with K2 Space is governed on the basis of merit, competence and qualifications and will not be influenced in any manner by race, color, religion, gender, national origin/ethnicity, veteran status, disability status, age, sexual orientation, gender identity, marital status, mental or physical disability or any other legally protected status.

K2 is building the largest and highest-power satellites ever flown, unlocking performance levels previously out of reach across every orbit. Backed by $450M from leading investors including Altimeter Capital, Redpoint Ventures, T. Rowe Price, Lightspeed Venture Partners, Alpine Space Ventures, and others – with an additional $500M in signed contracts across commercial and US government customers – we’re mass-producing the highest-power satellite platforms ever built for missions from LEO to deep space. The rise of heavy-lift launch vehicles is shifting the industry from an era of mass constraint to one of mass abundance, and we believe this new era demands a fundamentally different class of spacecraft. Engineered to survive the harshest radiation environments and to fully capitalize on today’s and tomorrow’s massive rockets, K2 satellites deliver unmatched capability at constellation scale and across multiple orbits. With multiple launches planned through 2026 and 2027, we're Building Bigger to develop the solar system and become a Kardashev Type II (K2) civilization. If you are a motivated individual who thrives in a fast-paced environment and you're excited about contributing to the success of a groundbreaking Series C space startup, we’d love for you to apply. The Role We are seeking a Senior ASIC Physical Design Engineer to help implement advanced SoCs that power next-generation satellite and space systems. In this role, you will contribute to the full physical design flow—from synthesis to GDSII—working closely with architecture, RTL, verification, and packaging teams. You’ll be a key contributor in achieving timing closure, optimizing PPA, and supporting design integration with external partners. You will be part of a collaborative design team developing state-of-the-art mixed-signal SoCs to be hosted on some of the largest, most powerful, rapidly designed and rapidly manufactured satellites ever deployed in space. In your first 6 months, you will develop and implement new SoC sub-systems for satellite communications and beyond. In your first two years, you will have contributed to developing cutting-edge SoCs that will fly in space.  Responsibilities - Execute the complete physical design flow for complex SoC blocks and top-level integration, including synthesis, floorplanning, place & route, CTS, STA, and physical verification. - Perform timing closure and optimization across multiple corners and modes using industry-standard tools. - Collaborate with front-end, verification, and DFT teams to ensure clean handoff and predictable convergence. - Work with external physical design service providers and internal leads to review deliverables, resolve issues, and ensure schedule alignment. - Develop and maintain scripts and automation to improve flow efficiency and consistency. - Support physical sign-off activities including DRC/LVS, IR drop, EM, and power analysis. - Assist in chip-level integration, ECOs, and tapeout preparation. - Contribute to methodology development, tool evaluation, and flow documentation. - Support your product through production and spaceflight. Required Qualifications  - Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field. - 5–10 years of experience in ASIC physical design for complex SoCs. - Hands-on experience with industry-standard tools (Synopsys ICC2/Fusion Compiler, Cadence Innovus, or equivalent). - Strong understanding of timing analysis, power optimization, and physical verification flows. - Experience with hierarchical or flat SoC design methodologies. - Familiarity with FinFET technologies. - Working knowledge of DFT, UPF/CPF power intent, and ECO implementation. - Strong problem-solving skills and ability to work cross-functionally in fast-paced environments. Preferred Qualifications  - Exposure to radiation-hardened or space-qualified ASICs. - Experience with chip-package co-design or advanced packaging (2.5D/3D). - Familiarity with physical design service vendor management or offshore collaboration. - Experience with sign-off through TSMC. - Experience with Gate-All-Around technologies. - Experience working in cross-functional, geographically distributed teams. Compensation and Benefits: - Base salary range for this role is $170,000 – $250,000 + equity in the company - Salary will be based on several factors including, but not limited to: knowledge and skills, education, and experience level - Comprehensive benefits package including paid time off, medical/dental/vision/ coverage, life insurance, paid parental leave, and many other perks If you don’t meet 100% of the preferred skills and experience, we encourage you to still apply! Building a spacecraft unlike any other requires a team unlike any other and non-traditional career twists and turns are encouraged! If you need a reasonable accommodation as part of your application for employment or interviews with us, please let us know. Export Compliance As defined in the ITAR, “U.S. Persons” include U.S. citizens, lawful permanent residents (i.e., Green Card holders), and certain protected individuals (e.g., refugees/asylees, American Samoans). Please consult with a knowledgeable advisor if you are unsure whether you are a “U.S. Person.” The person hired for this role will have access to information and items controlled by U.S. export control regulations, including the export control regulations outlined in the International Traffic in Arms Regulation (ITAR). The person hired for this role must therefore either be a “U.S. person” as defined by 22 C.F.R. § 120.15 or otherwise eligible for a federally issued export control license. Equal Opportunity K2 Space is an Equal Opportunity Employer; employment with K2 Space is governed on the basis of merit, competence and qualifications and will not be influenced in any manner by race, color, religion, gender, national origin/ethnicity, veteran status, disability status, age, sexual orientation, gender identity, marital status, mental or physical disability or any other legally protected status.

K2 is building the largest and highest-power satellites ever flown, unlocking performance levels previously out of reach across every orbit. Backed by $450M from leading investors including Altimeter Capital, Redpoint Ventures, T. Rowe Price, Lightspeed Venture Partners, Alpine Space Ventures, and others – with an additional $500M in signed contracts across commercial and US government customers – we’re mass-producing the highest-power satellite platforms ever built for missions from LEO to deep space. The rise of heavy-lift launch vehicles is shifting the industry from an era of mass constraint to one of mass abundance, and we believe this new era demands a fundamentally different class of spacecraft. Engineered to survive the harshest radiation environments and to fully capitalize on today’s and tomorrow’s massive rockets, K2 satellites deliver unmatched capability at constellation scale and across multiple orbits. With multiple launches planned through 2026 and 2027, we're Building Bigger to develop the solar system and become a Kardashev Type II (K2) civilization. If you are a motivated individual who thrives in a fast-paced environment and you're excited about contributing to the success of a groundbreaking Series C space startup, we’d love for you to apply. The Role We are seeking a Senior RFIC Layout Designer to drive the physical implementation of advanced RF and mixed-signal integrated circuits for next-generation satellite communication systems. This is a senior individual contributor role focused on hands-on layout execution and top-level integration, working closely with cross-functional teams to deliver high-performance silicon. Responsibilities - Execute high-quality layout for RF, analog, and mixed-signal blocks in advanced FinFET nodes (e.g., LNA, RF amplifiers, mixers, PLL, LO generation, ADC/DAC, baseband filters, bandgap/bias/LDO) - Contribute to top-level layout integration, including block placement, routing, power planning, and floorplanning. - Contribute to layout strategies to meet performance, area, power, reliability, and manufacturability targets. - Ensure robust implementation of matching and symmetry for sensitive RF/analog structures, and high-frequency routing and parasitic control. - Ensure robust implementation of EM/IR, ESD, latch-up, and reliability considerations - Collaborate closely with RF/analog designers, digital implementation teams, package/PCB engineers, and CAD to ensure seamless integration. - Participate in establishing review processes (layout reviews, signoff checks, and quality metrics) to ensure first-pass silicon success. - Drive full-chip physical signoff, including DRC/LVS/ERC closure, EM/IR and reliability verification. - Own tapeout readiness and interface with foundry and EDA partners as needed. Qualifications - 5+ years of RF/analog/mixed-signal layout experience. - Extensive hands-on experience with advanced FinFET process technologies (≤16nm preferred). - Proven track record of top-level SoC layout integration and successful silicon tapeouts. - Experience collaborating with distributed teams, including collaborating with external layout vendors. - Deep understanding of RF and analog layout techniques and device physics, including high-frequency effects, parasitics, and isolation strategies. - Extensive hands-on experience with power planning and full-chip physical architecture. - Strong proficiency with industry-standard tools. Nice to Have - Experience with high-frequency RF systems for wireless or satellite communications. - Experience working on large mixed-signal SoCs with significant digital content. - Exposure to reliability requirements for space or high-reliability applications. - Experience developing methodologies in a high-growth environment. Compensation and Benefits: - Base salary range for this role is $120,000 – $180,000 + equity in the company - Salary will be based on several factors including, but not limited to: knowledge and skills, education, and experience level - Comprehensive benefits package including paid time off, medical/dental/vision/ coverage, life insurance, paid parental leave, and many other perks If you don’t meet 100% of the preferred skills and experience, we encourage you to still apply! Building a spacecraft unlike any other requires a team unlike any other and non-traditional career twists and turns are encouraged! If you need a reasonable accommodation as part of your application for employment or interviews with us, please let us know. Export Compliance As defined in the ITAR, “U.S. Persons” include U.S. citizens, lawful permanent residents (i.e., Green Card holders), and certain protected individuals (e.g., refugees/asylees, American Samoans). Please consult with a knowledgeable advisor if you are unsure whether you are a “U.S. Person.” The person hired for this role will have access to information and items controlled by U.S. export control regulations, including the export control regulations outlined in the International Traffic in Arms Regulation (ITAR). The person hired for this role must therefore either be a “U.S. person” as defined by 22 C.F.R. § 120.15 or otherwise eligible for a federally issued export control license. Equal Opportunity K2 Space is an Equal Opportunity Employer; employment with K2 Space is governed on the basis of merit, competence and qualifications and will not be influenced in any manner by race, color, religion, gender, national origin/ethnicity, veteran status, disability status, age, sexual orientation, gender identity, marital status, mental or physical disability or any other legally protected status.

K2 is building the largest and highest-power satellites ever flown, unlocking performance levels previously out of reach across every orbit. Backed by $450M from leading investors including Altimeter Capital, Redpoint Ventures, T. Rowe Price, Lightspeed Venture Partners, Alpine Space Ventures, and others – with an additional $500M in signed contracts across commercial and US government customers – we’re mass-producing the highest-power satellite platforms ever built for missions from LEO to deep space. The rise of heavy-lift launch vehicles is shifting the industry from an era of mass constraint to one of mass abundance, and we believe this new era demands a fundamentally different class of spacecraft. Engineered to survive the harshest radiation environments and to fully capitalize on today’s and tomorrow’s massive rockets, K2 satellites deliver unmatched capability at constellation scale and across multiple orbits. With multiple launches planned through 2026 and 2027, we're Building Bigger to develop the solar system and become a Kardashev Type II (K2) civilization. If you are a motivated individual who thrives in a fast-paced environment and you're excited about contributing to the success of a groundbreaking Series C space startup, we’d love for you to apply. The Role We are looking for a Principal ASIC Physical Design Engineer to lead the implementation of complex SoCs for next-generation satellite and space systems. You will own the full physical design flow—from RTL handoff to GDSII—and collaborate closely with architecture, RTL design, DFT, and packaging teams. This role also involves managing external physical design partners, driving tool and flow decisions, and ensuring first-pass silicon success in advanced FinFET technologies. You’ll be a key contributor in achieving timing closure, optimizing PPA, and supporting design integration with external partners. You will be part of a collaborative design team developing state-of-the-art mixed-signal SoCs to be hosted on some of the largest, most powerful, rapidly designed and rapidly manufactured satellites ever deployed in space. In your first 6 months, you will develop and implement new SoC sub-systems for satellite communications and beyond. In your first two years, you will have contributed to developing cutting-edge SoCs that will fly in space. Responsibilities - Own the complete RTL-to-GDSII flow: synthesis, floorplanning, place & route, clock tree synthesis (CTS), static timing analysis (STA), physical verification (DRC/LVS), and sign-off. - Develop and maintain physical design methodologies, scripts, and automation to optimize performance, power, and area (PPA). - Collaborate with front-end and verification teams to ensure clean handoffs, timing closure, and efficient design iteration. - Drive timing closure across multiple voltage and process corners, including sign-off with foundry-qualified tools. - Partner with package, SI/PI, and test teams for package-aware floorplanning and chip-to-board integration. - Manage and technically guide external physical design partners and service vendors, ensuring alignment on milestones, deliverables, and quality standards. - Work with EDA vendors to debug and optimize tool flows, and evaluate new methodologies. - Support chip bring-up and debug through close collaboration with post-silicon and test teams. - Support your product through production and spaceflight. Required Qualifications - Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field. - 10+ years of experience in ASIC physical design for high-performance SoCs. - Proven end-to-end expertise in RTL-to-GDSII flows using industry tools (Synopsys, Cadence, or Siemens). - Strong hands-on experience with timing closure, IR drop analysis, and ECO implementation. - Deep understanding of physical design constraints for multi-clock, multi-voltage, and hierarchical SoCs. - Experience with advanced FinFET process nodes. - Prior experience managing or coordinating offshore/outsourced PD teams or vendors. - Familiarity with DFT integration, STA sign-off, and power domain implementation (UPF/CPF). - Excellent communication, leadership, and cross-functional collaboration skills. - Act as technical leader and subject-matter expert helping to teach, grow, and mentor others in the team. Preferred Qualifications - Exposure to radiation-hardened or space-qualified ASICs. - Experience with chip-package co-design or advanced packaging (2.5D/3D). - Familiarity with physical design service vendor management or offshore collaboration. - Experience driving tapeouts through TSMC. - Experience with Gate-All-Around technologies. - Experience working in cross-functional, geographically distributed teams. Compensation and Benefits: - Base salary range for this role is $190,000 – $280,000 + equity in the company - Salary will be based on several factors including, but not limited to: knowledge and skills, education, and experience level - Comprehensive benefits package including paid time off, medical/dental/vision/ coverage, life insurance, paid parental leave, and many other perks If you don’t meet 100% of the preferred skills and experience, we encourage you to still apply! Building a spacecraft unlike any other requires a team unlike any other and non-traditional career twists and turns are encouraged! If you need a reasonable accommodation as part of your application for employment or interviews with us, please let us know. Export Compliance As defined in the ITAR, “U.S. Persons” include U.S. citizens, lawful permanent residents (i.e., Green Card holders), and certain protected individuals (e.g., refugees/asylees, American Samoans). Please consult with a knowledgeable advisor if you are unsure whether you are a “U.S. Person.” The person hired for this role will have access to information and items controlled by U.S. export control regulations, including the export control regulations outlined in the International Traffic in Arms Regulation (ITAR). The person hired for this role must therefore either be a “U.S. person” as defined by 22 C.F.R. § 120.15 or otherwise eligible for a federally issued export control license. Equal Opportunity K2 Space is an Equal Opportunity Employer; employment with K2 Space is governed on the basis of merit, competence and qualifications and will not be influenced in any manner by race, color, religion, gender, national origin/ethnicity, veteran status, disability status, age, sexual orientation, gender identity, marital status, mental or physical disability or any other legally protected status.

K2 is building the largest and highest-power satellites ever flown, unlocking performance levels previously out of reach across every orbit. Backed by $450M from leading investors including Altimeter Capital, Redpoint Ventures, T. Rowe Price, Lightspeed Venture Partners, Alpine Space Ventures, and others – with an additional $500M in signed contracts across commercial and US government customers – we’re mass-producing the highest-power satellite platforms ever built for missions from LEO to deep space. The rise of heavy-lift launch vehicles is shifting the industry from an era of mass constraint to one of mass abundance, and we believe this new era demands a fundamentally different class of spacecraft. Engineered to survive the harshest radiation environments and to fully capitalize on today’s and tomorrow’s massive rockets, K2 satellites deliver unmatched capability at constellation scale and across multiple orbits. With multiple launches planned through 2026 and 2027, we're Building Bigger to develop the solar system and become a Kardashev Type II (K2) civilization. If you are a motivated individual who thrives in a fast-paced environment and you're excited about contributing to the success of a groundbreaking Series C space startup, we’d love for you to apply. The Role We are seeking a Senior Mixed-Signal Behavioral Modeling Engineer to own the creation of behavioral modeling and drive mixed-signal verification methodology from the ground up. You will be part of a collaborative design team developing state-of-the-art mixed-signal SoCs to be hosted on some of the largest, most powerful, rapidly designed and rapidly manufactured satellites ever deployed in space. Your work will directly influence top-level integration and silicon tapeout success. This is a high-impact, technical role with significant ownership across modeling, methodology, verification, and cross-functional alignment with RF, analog, and digital teams. Responsibilities - Develop high-level behavioral models for analog and mixed-signal IP (ADCs, DACs, PLLs, LDOs, RF front-end blocks, biasing, amplifiers, etc.). - Create abstracted models using Verilog, Verilog-AMS, or SystemVerilog. - Develop regression infrastructure and mixed-signal testbenches enabling co-simulation (digital + analog). - Integrate AMS models into digital verification environments (UVM-based). - Define and build the mixed-signal verification methodology for top-level SoC and subsystem verification. - Support architectural exploration through early-phase modeling and system-level simulations. - Collaborate with analog/RF designers to capture real-world analog behaviors and map them into accurate behavioral abstractions. - Work with digital and verification teams to ensure seamless integration of AMS models. - Provide modeling and verification insights during architectural reviews, PDR/CDR, and silicon bring-up. - Act as technical leader and subject-matter expert.  Required Qualifications  - M.S. or Ph.D. in Electrical Engineering, Computer Engineering, or related field. - 5+ years of experience in analog/mixed-signal modeling and/or AMS verification. - Hands-on experience with SystemVerilog, Verilog-AMS, wreal/RNM, or equivalent modeling languages. - Strong understanding of analog/mixed-signal circuits (PLLs, LDOs, ADC/DACs, RF/IF paths, clocking, amplifiers). - Experience with mixed-signal co-simulation environments (Cadence AMS Designer, Synopsys VCS AMS, or similar). Preferred Qualifications  - Experience building AMS verification methodologies from scratch. - Familiarity with UVM-based verification and digital design flows. - Knowledge of signal processing theory, RF system modeling, or communication systems. - Experience with MATLAB/Simulink, Python modeling, or SystemC AMS for high-level architectural modeling. - Experience working in cross-functional, geographically distributed teams. Compensation and Benefits: - Base salary range for this role is $160,000 – $230,000 + equity in the company - Salary will be based on several factors including, but not limited to: knowledge and skills, education, and experience level - Comprehensive benefits package including paid time off, medical/dental/vision/ coverage, life insurance, paid parental leave, and many other perks If you don’t meet 100% of the preferred skills and experience, we encourage you to still apply! Building a spacecraft unlike any other requires a team unlike any other and non-traditional career twists and turns are encouraged! If you need a reasonable accommodation as part of your application for employment or interviews with us, please let us know. Export Compliance As defined in the ITAR, “U.S. Persons” include U.S. citizens, lawful permanent residents (i.e., Green Card holders), and certain protected individuals (e.g., refugees/asylees, American Samoans). Please consult with a knowledgeable advisor if you are unsure whether you are a “U.S. Person.” The person hired for this role will have access to information and items controlled by U.S. export control regulations, including the export control regulations outlined in the International Traffic in Arms Regulation (ITAR). The person hired for this role must therefore either be a “U.S. person” as defined by 22 C.F.R. § 120.15 or otherwise eligible for a federally issued export control license. Equal Opportunity K2 Space is an Equal Opportunity Employer; employment with K2 Space is governed on the basis of merit, competence and qualifications and will not be influenced in any manner by race, color, religion, gender, national origin/ethnicity, veteran status, disability status, age, sexual orientation, gender identity, marital status, mental or physical disability or any other legally protected status.

K2 is building the largest and highest-power satellites ever flown, unlocking performance levels previously out of reach across every orbit. Backed by $450M from leading investors including Altimeter Capital, Redpoint Ventures, T. Rowe Price, Lightspeed Venture Partners, Alpine Space Ventures, and others – with an additional $500M in signed contracts across commercial and US government customers – we’re mass-producing the highest-power satellite platforms ever built for missions from LEO to deep space. The rise of heavy-lift launch vehicles is shifting the industry from an era of mass constraint to one of mass abundance, and we believe this new era demands a fundamentally different class of spacecraft. Engineered to survive the harshest radiation environments and to fully capitalize on today’s and tomorrow’s massive rockets, K2 satellites deliver unmatched capability at constellation scale and across multiple orbits. With multiple launches planned through 2026 and 2027, we're Building Bigger to develop the solar system and become a Kardashev Type II (K2) civilization. If you are a motivated individual who thrives in a fast-paced environment and you're excited about contributing to the success of a groundbreaking Series C space startup, we’d love for you to apply. The Role As a Principal GNC engineer, you will be a core driver of the overall spacecraft GNC architecture. You will execute detailed trade studies to find new and novel ways to implement the spacecraft’s guidance, attitude control, and attitude and orbit estimation systems. You will anticipate company needs and stand-up infrastructure to support the core and future business. In the first 3 months, you will own and execute the Verification and Validation plan for the GNC stack, driving the system to flight readiness via a robust and thorough analysis of vehicle performance in both nominal and off nominal environments. This push for flight readiness will motivate thorough analysis, leading to updates to both the GNC stack and the K2 6-DOF simulation. The expectation is that all GNC team members commit code to the 6-DOF sim as well as owning a portion of the GNC flight software. In the first 6 months, you will support launch and on orbit operations of the first full demonstration of the K2 spacecraft bus – the Mega. In parallel, you will scope and support the block 2 upgrades of the GNC stack and 6-DOF sim, taking lessons learned from on orbit operations to increase the fidelity of the simulation and the vehicle performance of the GNC stack. In the first year, you will own the planning and development of future tooling to support GNC in defining vehicle level capabilities, especially for future missions. This includes mission design, precision pointing and controls analysis, constellation development, and 6-DOF simulation development. Responsibilities - Work with other engineering leads to set the direction and develop novel vehicle architecture - Develop novel algorithms for precise pointing of very large, flexible structures in earth orbit and beyond - Develop novel slewing algorithms of very large, flexible structures in earth orbit and beyond - Develop simulation and modeling tools to support vehicle and GNC trade studies. This includes mission design, controls analysis, and 6-DOF simulation development. - Integral to building the GNC organization by recruiting, hiring, and mentoring other engineers Qualifications - Experience with GNC actuator or sensor sizing, selection, and system design - Experience with implementing attitude control and/or estimation algorithms on spacecraft - Experience with verification and validation of GNC flight software in an integrated environment, leveraging 6-DOF simulation and HITL testing. - Experience with early-stage spacecraft conceptual design, i.e. “clean sheet” design work - Experience with Python, Julia, C/C++, or Matlab for algorithm development, implementation, and simulation Nice to Have - Experience with control algorithm development - Experience with reaction wheel, control moment gyroscope, or thruster sizing and algorithm implementation - Experience with navigation, specifically Extended Kalman Filters - Experience with trajectory analysis, modeling, and mission design Compensation and Benefits: - Base salary range for this role is $190,000 - $260,000 + equity in the company - Salary will be based on several factors including, but not limited to: knowledge and skills, education, and experience level - Comprehensive benefits package including paid time off, medical/dental/vision coverage, life insurance, paid parental leave, and many other perks If you don’t meet 100% of the preferred skills and experience, we encourage you to still apply! Building a spacecraft unlike any other requires a team unlike any other and non-traditional career twists and turns are encouraged! If you need a reasonable accommodation as part of your application for employment or interviews with us, please let us know. Export Compliance As defined in the ITAR, “U.S. Persons” include U.S. citizens, lawful permanent residents (i.e., Green Card holders), and certain protected individuals (e.g., refugees/asylees, American Samoans). Please consult with a knowledgeable advisor if you are unsure whether you are a “U.S. Person.” The person hired for this role will have access to information and items controlled by U.S. export control regulations, including the export control regulations outlined in the International Traffic in Arms Regulation (ITAR). The person hired for this role must therefore either be a “U.S. person” as defined by 22 C.F.R. § 120.15 or otherwise eligible for a federally issued export control license. Equal Opportunity K2 Space is an Equal Opportunity Employer; employment with K2 Space is governed on the basis of merit, competence and qualifications and will not be influenced in any manner by race, color, religion, gender, national origin/ethnicity, veteran status, disability status, age, sexual orientation, gender identity, marital status, mental or physical disability or any other legally protected status.