• Participate in the design, development, and operation of several key embedded software capabilities on the Lime vehicles and related products. • Be the voice of customers for engineering excellence within the team and influence team roadmap decisions. • Provide feedback in the peer review process and effectively communicate with technical leadership. • Own unique embedded software functions through design, implementation (in C, C++, RUST etc), testing, and integration in an embedded Linux or real-time operating system (RTOS) environment. • Learn and master multiple components including networking(LTE)/WiFi, motor control, Over-the-Air (OTA) software updates, and various sensors. • Write software to interact with devices/electronics using I2C, SPI, CAN, UART, etc. • Work closely with hardware teams to support board design, bring-up, and verification, as well as integration and testing during various phases of product development including proof of concept.

• Driving DPU hardware and software integration into Akamai compute and GPU server platforms, including PCIe, networking, storage, and manageability interfaces. • Planning and executing validation for DPU platforms, including functional, performance, interoperability, stress, and reliability testing for data-center scale use cases. • Implementing and validating networking and offload features such as RDMA/RoCE, L2/L3/L4 Ethernet/IP forwarding, SR-IOV/virtio-net/vDPA, overlay networks, and congestion control behaviors. • Developing automation, scripts, and test tooling to exercise DPUs, collect telemetry at scale, and turn results into requirements. • Collaborating closely with cross-functional teams to translate workload and SLO requirements into configurations and test plans. • Working with vendors to evaluate new DPU generations, firmware and feature updates, and trade-offs between performance, efficiency, supply continuity, and TCO.

This description is a summary of our understanding of the job description. Click on 'Apply' button to find out more. Role Description We are seeking a Principal ASIC Design Verification Engineer whose role will be to verify the functionality, performance, and robustness of our custom silicon designs. You will help define the verification approach, contribute to methodology, and work closely with architecture, RTL design, DFT, firmware, physical design, and silicon validation engineers. This is a hands-on role with high ownership, deep technical engagement, and the opportunity to shape first-generation silicon. Responsibilities - Develop and execute verification plans for block-level, subsystem-level, and full-chip environments. - Build SystemVerilog/UVM test benches, including agents, monitors, scoreboards, checkers, and coverage models. - Write SystemVerilog Assertions (SVA) and integrate formal verification where appropriate. - Drive constrained-random and directed testing strategies to validate functionality, corner cases, and stress scenarios. - Run simulations, triage failures, drive root-cause analysis, and collaborate with RTL designers to resolve issues. - Implement and maintain functional coverage, code coverage, assertion coverage, and ensure coverage closure for sign-off. - Manage regression testing, simulation farms, and CI pipelines to ensure high test throughput and fast debug iterations. - Participate in design reviews, microarchitecture discussions, and influence design-for-verification (DFV) best practices. - Work closely with architecture, RTL design, DFT, firmware, physical design, and silicon validation engineers to ensure end-to-end coverage and test. - Support silicon bring-up and post-silicon validation through test reuse, diagnostics, and debug analysis. - Participate in ASIC team interviews. - Drive advancement of DV methodologies and improvements. - Manage external IP providers and verification partners when needed. - Take lead on large and/or complex systems. Qualifications - B.S. or M.S. in Electrical Engineering, Computer Engineering, or related field. - 10+ years of experience in ASIC/SoC verification. - Solid understanding of SystemVerilog, digital logic, RTL design, DFT, and hardware design and verification flows. - Proficiency with several simulation (VCS, Xcelium, Questa), waveform debug (Verdi, SimVision), coverage tools, and scripting languages (ex: Python, Perl, TCL). - Experience with test planning, UVM-based testbench development, constrained-random testing, functional coverage, and SystemVerilog assertions. - Experience with regression management, coverage analysis, revision control (ex: Git), CI/CD automation, and gate-level simulation. - Experience with developing and integrating reference models. - Experience with embedded processor-based designs and firmware/bare metal coding (ex: C, C++). - Understanding of many industry-standard interfaces (ex: APB/AHB/AXI). - Involvement in post-silicon validation planning and execution. Preferred Qualifications - Experience with low power verification. - Experience with analog behavioral models. - Familiarity with physical design flows. - Experience working in cross-functional, geographically distributed teams. - Experience in space, telecom, or RF/digital mixed systems is a plus. Benefits - Base salary range for this role is $190,000 – $285,000 + equity in the company. - Salary will be based on several factors including, but not limited to: knowledge and skills, education, and experience level. - Comprehensive benefits package including paid time off, medical/dental/vision coverage, life insurance, paid parental leave, and many other perks.

This description is a summary of our understanding of the job description. Click on 'Apply' button to find out more. Role Description We are seeking a Senior ASIC Design Verification Engineer whose role will be to verify the functionality, performance, and robustness of our custom silicon designs. You will help define the verification approach, contribute to methodology, and work closely with architecture, RTL design, DFT, firmware, physical design, and silicon validation engineers. This is a hands-on role with high ownership, deep technical engagement, and the opportunity to shape first-generation silicon. Responsibilities - Develop and execute verification plans for block-level, subsystem-level, and full-chip environments. - Build SystemVerilog/UVM test benches, including agents, monitors, scoreboards, checkers, and coverage models. - Write SystemVerilog Assertions (SVA) and integrate formal verification where appropriate. - Drive constrained-random and directed testing strategies to validate functionality, corner cases, and stress scenarios. - Run simulations, triage failures, drive root-cause analysis, and collaborate with RTL designers to resolve issues. - Implement and maintain functional coverage, code coverage, assertion coverage, and ensure coverage closure for sign-off. - Manage regression testing, simulation farms, and CI pipelines to ensure high test throughput and fast debug iterations. - Participate in design reviews, microarchitecture discussions, and influence design-for-verification (DFV) best practices. - Work closely with architecture, RTL design, DFT, firmware, physical design, and silicon validation engineers to ensure end-to-end coverage and test. - Support silicon bring-up and post-silicon validation through test reuse, diagnostics, and debug analysis. - Participate in ASIC team interviews. - Contribute to advancement of DV methodologies and improvements. - Engage external IP providers and verification partners when needed. Qualifications - B.S. or M.S. in Electrical Engineering, Computer Engineering, or related field. - 5+ years of experience in ASIC/SoC verification. - Solid understanding of SystemVerilog, digital logic, RTL design, and hardware verification flows. - Proficiency with a simulation (VCS, Xcelium, Questa), waveform debug (Verdi, SimVision), coverage tool, and scripting languages (ex: Python, Perl, TCL). - Experience with test planning, UVM-based testbench development, constrained-random testing, functional coverage, and SystemVerilog assertions. - Experience with regression management, coverage analysis, revision control (Git), and CI/CD automation. - Understanding of several industry-standard interfaces (ex: APB/AHB/AXI). - Familiarity with embedded processor-based designs and firmware/bare metal coding (ex: C, C++). Preferred Qualifications - Experience with developing and integrating reference models. - Understanding of low power verification. - Familiarity with gate-level simulation and analog behavioral models. - Involvement in post-silicon validation planning and execution. - Experience working in cross-functional, geographically distributed teams. - Experience in space, telecom, or RF/digital mixed systems is a plus. Compensation and Benefits - Base salary range for this role is $170,000 – $250,000 + equity in the company. - Salary will be based on several factors including, but not limited to: knowledge and skills, education, and experience level. - Comprehensive benefits package including paid time off, medical/dental/vision coverage, life insurance, paid parental leave, and many other perks.