This description is a summary of our understanding of the job description. Click on 'Apply' button to find out more. Role Description We are seeking a Senior ASIC Design Verification Engineer whose role will be to verify the functionality, performance, and robustness of our custom silicon designs. You will help define the verification approach, contribute to methodology, and work closely with architecture, RTL design, DFT, firmware, physical design, and silicon validation engineers. This is a hands-on role with high ownership, deep technical engagement, and the opportunity to shape first-generation silicon. Responsibilities - Develop and execute verification plans for block-level, subsystem-level, and full-chip environments. - Build SystemVerilog/UVM test benches, including agents, monitors, scoreboards, checkers, and coverage models. - Write SystemVerilog Assertions (SVA) and integrate formal verification where appropriate. - Drive constrained-random and directed testing strategies to validate functionality, corner cases, and stress scenarios. - Run simulations, triage failures, drive root-cause analysis, and collaborate with RTL designers to resolve issues. - Implement and maintain functional coverage, code coverage, assertion coverage, and ensure coverage closure for sign-off. - Manage regression testing, simulation farms, and CI pipelines to ensure high test throughput and fast debug iterations. - Participate in design reviews, microarchitecture discussions, and influence design-for-verification (DFV) best practices. - Work closely with architecture, RTL design, DFT, firmware, physical design, and silicon validation engineers to ensure end-to-end coverage and test. - Support silicon bring-up and post-silicon validation through test reuse, diagnostics, and debug analysis. - Participate in ASIC team interviews. - Contribute to advancement of DV methodologies and improvements. - Engage external IP providers and verification partners when needed. Qualifications - B.S. or M.S. in Electrical Engineering, Computer Engineering, or related field. - 5+ years of experience in ASIC/SoC verification. - Solid understanding of SystemVerilog, digital logic, RTL design, and hardware verification flows. - Proficiency with a simulation (VCS, Xcelium, Questa), waveform debug (Verdi, SimVision), coverage tool, and scripting languages (ex: Python, Perl, TCL). - Experience with test planning, UVM-based testbench development, constrained-random testing, functional coverage, and SystemVerilog assertions. - Experience with regression management, coverage analysis, revision control (Git), and CI/CD automation. - Understanding of several industry-standard interfaces (ex: APB/AHB/AXI). - Familiarity with embedded processor-based designs and firmware/bare metal coding (ex: C, C++). Preferred Qualifications - Experience with developing and integrating reference models. - Understanding of low power verification. - Familiarity with gate-level simulation and analog behavioral models. - Involvement in post-silicon validation planning and execution. - Experience working in cross-functional, geographically distributed teams. - Experience in space, telecom, or RF/digital mixed systems is a plus. Compensation and Benefits - Base salary range for this role is $170,000 – $250,000 + equity in the company. - Salary will be based on several factors including, but not limited to: knowledge and skills, education, and experience level. - Comprehensive benefits package including paid time off, medical/dental/vision coverage, life insurance, paid parental leave, and many other perks.

Verification Engineer Who we are: We are a stealth-mode startup building foundational technology to address performance, scalability, and resiliency challenges in large-scale AI data center clusters. We are backed by top-tier VC firms and notable angel investors. The company is led by experienced builders and operators who have founded companies, taken them to scale, and exited successfully. We work with a strong sense of unity and shared responsibility, and we expect trust, integrity, and respect in how we collaborate and make decisions. We hold ourselves accountable to one another and to the quality of the work we deliver. Headquartered in Silicon Valley, we operate across a mix of remote and on-site locations in the U.S. and Canada. We aim to create an environment where people are treated fairly, supported in their growth, and are empowered to do meaningful work alongside others who take the craft seriously. What we need: An experienced RTL Verification Engineer responsible for ensuring the functionality, correctness, and quality of complex digital designs across ASIC and FPGA platforms. This role focuses on building robust verification environments, executing coverage-driven verification plans, and working closely with RTL design engineers to deliver reliable, high-quality silicon. The ideal candidate has deep hands-on experience with SystemVerilog, UVM (or similar methodologies), and modern verification workflows, and is comfortable driving verification efforts from planning through closure. Key Responsibilities: · Develop, implement, and maintain RTL verification environments using UVM or equivalent methodologies · Create and execute coverage-driven verification plans aligned with design specifications · Develop directed and constrained-random test cases and sequences to validate functionality and identify corner cases · Analyze simulation results, debug complex verification and design issues, and perform root-cause analysis in collaboration with RTL design engineers · Implement and track functional and code coverage, driving verification to closure · Develop reusable verification components and write SystemVerilog Assertions (SVA) · Participate in design and verification reviews, providing input on design testability, correctness, and optimization · Automate regression testing and enhance verification infrastructure using Python and scripting · Contribute to continuous improvement of verification processes, tools, and methodologies Required Skills and Qualifications: · Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field · 7+ years of experience in digital design verification · Strong hands-on experience with UVM-based or similar verification methodologies · Proficiency in SystemVerilog, UVM, and Python · Experience with industry-standard EDA tools (e.g., Synopsys VCS, Siemens/Mentor Questa, Cadence Xcelium) · Solid understanding of digital design fundamentals · Experience verifying standard bus and interconnect protocols such as AXI, AXI-S, and APB · Experience with high-speed communication protocols including PCIe, Ethernet (10G/40G/100G), SPI, and I²C · Strong analytical and problem-solving skills · Clear written and verbal communication skills for cross-functional collaboration · High attention to detail and ability to deliver reliable, high-quality verification outcomes · Ability to work independently and manage tasks to completion Desired Skills: · Experience with formal verification techniques and tools · Experience verifying processor subsystems or SoC-level designs Compensation: Target base salary for this role is $160,000 – $220,000 per year, plus meaningful equity, benefits, and 401(k). Salary ranges are determined by role, level, experience, and location. #LI-EW1

Advanced Packaging Engineer – Design & Signal Integrity Who we are: We are a stealth-mode startup building foundational technology to address performance, scalability, and resiliency challenges in large-scale AI data center clusters. We are backed by top-tier VC firms and notable angel investors. The company is led by experienced builders and operators who have founded companies, taken them to scale, and exited successfully. We work with a strong sense of unity and shared responsibility, and we expect trust, integrity, and respect in how we collaborate and make decisions. We hold ourselves accountable to one another and to the quality of the work we deliver. Headquartered in Silicon Valley, we operate across a mix of remote and on-site locations in the U.S. and Canada. We aim to create an environment where people are treated fairly, supported in their growth, and are empowered to do meaningful work alongside others who take the craft seriously. What we need: We are looking for an Electrical Engineer for ASIC Package Design & Signal Integrity to design, model, and validate advanced semiconductor packages to ensure high-speed data and power integrity, focusing on minimizing noise, reflections, and ensuring manufacturability for custom chips Key tasks include running simulations (using tools like Ansys HFSS, Cadence Sigrity, ADS), defining package specifications, collaborating with IC designers and suppliers, analyzing power delivery networks (PDN), and debugging hardware for high-speed interfaces (UCIe,Ethernet). Key Responsibilities: - Package Development: Select and design optimal multi-die IC package types considering electrical performance, cost, and manufacturability. - Signal Integrity (SI) Analysis: Perform pre- and post-layout simulations (e.g., eye diagrams, crosstalk) for high-speed interfaces (UCIe, D2D, high-speed serdes). - Power Integrity (PI) Analysis: Model and simulate Power Delivery Networks (PDN) for low-voltage, high-current supplies, including AC/DC analysis and IR drop. - Modeling & Simulation: Develop accurate simulation models (S-parameters, IBIS-AMI) for packages, PCBs, and sockets. - Cross-Functional Collaboration: Work with IC design, physical design, board layout, and marketing teams to define requirements and resolve issues. - Layout Review: Guide PCB/package layout, reviewing stack-ups, trace routing, and component placement for optimal SI/PI performance. - Lab Validation: Support hardware bring-up, debug, and correlation between simulation/models and physical measurements. - Technology Development: Research and implement new SI/PI techniques and tools for next-generation products. Required Skills and Qualifications: - B.S./M.S. in Electrical Engineering or related field. - Strong understanding of EM theory, transmission lines, and signal integrity principles. - Expertise in SI/PI simulation tools (Keysight ADS, Ansys HFSS, Cadence Sigrity/PowerSI). - Experience with high-speed interfaces (UCIe, D2D, Ethernet). - Knowledge of board materials, stack-up design, and constraint management. - Hands-on experience with lab equipment (VNA, TDR, Oscilloscope). - Proficiency in programming/automation (Python, Matlab) is a plus. - Experience in Multi-Die package designs using standard UCIe (AP and/or SP) - Experience selecting and managing sub-contractors - Experience interfacing with TSMC for packaging options (bumping) Compensation: Target base salary for this role is $160,000 - $220,000 per year + meaningful equity + benefits + 401k. Our salary ranges are determined by role, level, experience, and location. #LI-EW1

Senior FPGA Design Engineer Who we are: We are a stealth-mode startup building foundational technology to address performance, scalability, and resiliency challenges in large-scale AI data center clusters. We are backed by top-tier VC firms and notable angel investors. The company is led by experienced builders and operators who have founded companies, taken them to scale, and exited successfully. We work with a strong sense of unity and shared responsibility, and we expect trust, integrity, and respect in how we collaborate and make decisions. We hold ourselves accountable to one another and to the quality of the work we deliver. Headquartered in Silicon Valley, we operate across a mix of remote and on-site locations in the U.S. and Canada. We aim to create an environment where people are treated fairly, supported in their growth, and are empowered to do meaningful work alongside others who take the craft seriously. What we need: A Senior FPGA Design Engineer to design, develop, verify, and integrate complex digital logic systems on high-performance FPGA platforms. This role focuses on AMD/Xilinx architectures including Virtex and Versal, and spans the full FPGA development lifecycle from architecture through lab bring-up and deployment. Key Responsibilities: - Translate high-level system requirements into FPGA architectural and micro-architectural specifications - Develop robust, clean, and maintainable RTL code using VHDL, Verilog, and SystemVerilog - Create and utilize simulation testbenches using tools such as XCelium and Vivado to verify functionality and performance - Perform synthesis, place-and-route, and static timing analysis using Xilinx tools (Vivado, ISE) - Optimize designs for performance, power, and area (PPA) - Bring up FPGAs on custom PCBs and debug using oscilloscopes, logic analyzers, and on-chip debugging tools (Vivado Logic Analyzer) - Develop scripts to update and download FPGA clusters in live server environments - Collaborate with hardware, software, systems, and verification engineers to ensure system integration and validation - Create and maintain design specifications, test plans, and test results documentation - Build and maintain FPGA software environments using Vitis, including toolchains, reference drivers, and processor core environments Required Skills and Qualifications: - Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field - Proficiency with AMD/Xilinx FPGA platforms - Proficiency with Vivado, Vitis, and ISE development environments - Strong understanding of digital design principles, high-speed digital design, signal integrity, and clock domain crossing (CDC) - Experience with PCIe, Ethernet (10G/40G/100G), AXI, AXI-S, SPI, and I2C - Experience instantiating soft CPU cores such as RISC-V and using hard cores in SoC FPGAs - Experience integrating external memory including HBM and DDR Desired Skills: - Familiarity with C, C++, and Python for test scripting or embedded processor integration - Experience using version control systems such as Git or Perforce Compensation: Target base salary for this role is $160,000 – $220,000 per year, plus meaningful equity, benefits, and 401(k). Salary ranges are determined by role, experience, and location. #LI-EW1