Axelera AI

Role Description Axelera AI is seeking a talented Senior/Staff Engineer – Computing Architecture to design and develop the next generation of AI computing systems. In this critical role, you will work closely with hardware, software, and product teams to define architectural requirements, optimize system performance, and ensure scalability for our AI solutions. As a Computing Architecture Engineer, you will contribute to the conceptualization, specification, and implementation of advanced computing architectures, enabling Axelera AI to deliver cutting-edge solutions that meet the demanding needs of our customers. - Architecture Design: Define and develop computing architectures for AI accelerators. - Performance Optimization: Analyze and optimize computational workloads, ensuring low power consumption, high efficiency, and maximum performance for AI applications. - Technology Leadership: Drive innovation in architectural design by evaluating emerging technologies, industry trends, and academic advancements. - Cross-Functional Collaboration: Work with hardware, software, and product teams to translate system requirements into architectural solutions that balance performance, cost, and power. - System Modeling & Tooling Development: Develop simulation and modeling tools to validate architectural designs and predict system performance across target AI workloads. - Mentorship: Provide technical guidance and mentorship to junior engineers, fostering a culture of excellence and innovation within the team. Qualifications - Master’s or PhD in Computer Engineering, Electrical Engineering, or a related field. - 5+ years of experience in computing architecture or system design, preferably within AI, semiconductor, or computing domains. - Strong expertise in AI accelerator designs, including neural processing units (NPUs) or graphics processing units (GPUs). - Proficiency in architectural modeling, simulation tools, and performance analysis frameworks. - Proficiency in Python or C++ programming with a strong understanding of language features and best practices. - Deep understanding of state-of-the-art AI inference workloads, algorithms, and dataflow. - Proven track record of delivering complex computing architectures from concept to implementation. - Strong communication and collaboration skills, with the ability to work in a multidisciplinary and global environment. Requirements - Familiarity with the modern IC design flow from architecture to GDSII to communicate with silicon implementation stakeholders. - Familiarity with parallel programming models, e.g. via CUDA or similar APIs. - Hands-on experience with low-level programming close to hardware and understanding of computer system architecture basics. - Experience with AI compilation frameworks such as MLIR and/or TVM. Benefits - Attractive compensation package, including a pension plan and extensive employee insurances. - Option to get company shares. - Open culture that supports creativity and continual innovation. - Collaborative ownership and freedom with responsibility.

Role Description We are looking for a Senior Platform Architect to own the platform-level architecture of our scale-up and scale-out systems as we grow from single-accelerator products to server- and rack-level deployments. In this role you will define how our current and next-generation accelerators come together as high-performance platforms. You own how accelerators are composed into systems to execute workloads effectively, defining system topology, host integration, memory organization and platform-level requirements to achieve performance, scalability and operability. The role is in close collaboration with the AI Infrastructure Systems division that builds our board- and system-level products, as well as with the broader architecture teams, and the silicon and software divisions. Finally, you will engage directly with strategic customers and ecosystem partners on architecture requirements and technical alignment. - Define the platform-level architecture of scale-up and scale-out fabrics across our accelerator product line, from single-node systems through to rack level deployments. - Specify physical interconnect infrastructure — defining the architectural requirements and trade-offs that the AI Infrastructure Systems division executes against, including how interconnect characteristics impact system-level workload performance. - Help translate workload and performance requirements into concrete system-level architecture and interconnect specifications. - Define host integration, covering PCIe, CXL and memory attachment, and the system-level memory organization across the platform. - Own platform performance, power, cost and scalability, ensuring scale-up and scale-out designs sustain target performance as systems grow from single nodes to large clusters. - Define operability and RAS (reliability, availability, serviceability) requirements so platforms are manageable and dependable in production. - Take a leading technical role in the system architecture team, interfacing directly with key partners and internal stakeholders to align architecture decisions. - Drive methodology and best practices for platform-level design as the team scales. Qualifications - Significant experience (5+ years) in system, platform, or hardware architecture, with a strong track record at server and/or rack scale. - Core knowledge in scale-up and scale-out system design, distributed workload mapping, functional partitioning, and interconnect/fabric architecture. - Deep, hands-on understanding of Ethernet, UALink, optical, and switched-fabric technologies, and the ability to reason about their system-level performance trade-offs. - Ability to connect workload characteristics to hardware architecture and to quantify the impact of design choices on end-to-end performance. - Demonstrated ability to lead and collaborate across multidisciplinary teams and to interface effectively with partners and senior stakeholders. - Strong problem-solving skills, a collaborative mindset, and a passion for building systems at scale. Requirements - Experience architecting AI/HPC accelerator systems. - Familiarity with distributed training/inference workloads. - Exposure to data-center-scale deployment. Benefits - Attractive compensation package, including a pension plan and extensive employee insurances. - Option to get company shares. - Open culture that supports creativity and continual innovation. - Collaborative ownership and freedom with responsibility. Location - Work from one of our Axelera AI offices (Leuven in Belgium, Amsterdam and Eindhoven in the Netherlands, Zurich in Switzerland, Florence and Milan in Italy or Bristol in the United Kingdom). - Work fully remotely from any European country (incl. the UK) you are already in. - Relocate with us and work from Italy (Florence or Milan) or the Netherlands (Amsterdam or Eindhoven). - Priority will be given to candidates who are interested in being based in Belgium or Italy.

Role Description As a Senior Advanced Packaging & Power Delivery Engineer at Axelera AI, you will play a pivotal role in shaping the silicon and packaging architecture of our next-generation AI accelerators. You will own power-delivery design across the full stack - from on-die power grids to package and PCB PDN - and bring deep expertise in advanced packaging technologies to help us scale from today's products to tomorrow's multi-chiplet, 3D-integrated systems. Working within our R&D Custom Design team and collaborating closely with Silicon Engineering and AI Integrated Systems, you will be at the intersection of analog design, packaging innovation, and product delivery - with real ownership and direct impact on the chips we ship. - Own power-delivery design end to end, from on-die power grids to package and PCB PDN design and analysis. - Lead advanced packaging architecture decisions for 2.5D/3D stacking, multi-chiplet integration, and interposer/substrate co-design. - Perform SI/PI verification and sign-off across the full stack, ensuring power integrity and signal integrity targets are met. - Collaborate with the AIIS and Silicon Engineering teams to align power delivery and packaging solutions with product and silicon requirements. - Support thermal and integration reviews for current and future products. - Develop and maintain power-delivery methodology, flows, and design guidelines within the Custom Design toolchain. - Identify and mitigate single-point-of-failure risks in SI/PI workstreams; mentor and grow the team's packaging expertise. - Engage with external partners, substrate/interposer vendors, and OSAT houses to co-develop advanced packaging solutions. Qualifications - Bachelor’s or Master’s degree in Electrical Engineering, Microelectronics, or a related field; PhD is a plus. - 7+ years of experience in power delivery and/or advanced packaging design in a semiconductor or deep-tech environment. - Demonstrated expertise in on-die power grid design and package/PCB PDN analysis. - Hands-on experience with 2.5D and/or 3D IC packaging technologies, multi-chiplet integration, and interposer/substrate co-design. - Proficiency with industry-standard EDA tools for power integrity, PDN simulation, and package design. - Ability to work cross-functionally and communicate complex technical trade-offs to diverse stakeholder groups. - Strong written and spoken English communication skills. Requirements - Experience with SI/PI verification and sign-off methodologies. - Familiarity with thermal modeling and co-simulation for integrated packages. - Exposure to AI accelerator or custom ASIC design flows. - Experience collaborating with OSAT partners, substrate vendors, or research institutes (e.g., imec). - Knowledge of advanced node custom and analog design practices. Benefits - Attractive compensation package, including a pension plan and extensive employee insurances. - Option to get company shares. - Open culture that supports creativity and continual innovation. - Collaborative ownership and freedom with responsibility. - Commitment to cultivating a warm and inclusive environment that empowers and celebrates every member of our team.

• Act as the primary technical point of contact for ODM partners adopting Axelera PCIe accelerator cards, M.2 modules, and AI SBCs into their systems. • Guide partners through hardware integration: compatibility, power budget, cooling, mechanical clearances, and BIOS/firmware settings. • Support partner bring-up: OS/driver installation, Voyager SDK deployment, and first-inference validation on customer platforms. • Produce and maintain integration guides, application notes, and FAQs tailored to key ODM accounts. • Provide on-site or remote support to CMs during Mass Production Introduction (MPI) phases, including first-article inspection and pilot-run reviews. • Review and validate CM production test procedures against Axelera ATE/ICT requirements; escalate deviations to the AIS engineering team. • Own in-field production defect triage: collect failure evidence, replicate issues on bench, and drive root-cause analysis in collaboration with R&D engineers. • Maintain a defect log and track corrective/preventive actions (CAPA) through to closure. • Coordinate with power component suppliers (DCDC converters, PMUs, DDR, passive components) on qualification questions and field-reported anomalies. • Perform bench characterisation of power-related issues (efficiency, regulation, transient response) and communicate findings to internal power integrity engineers. • Support BOM change evaluations for sourced alternatives, providing electrical equivalency data to the AIS team. • Contribute to the qualification of new components (power ICs, passives, memory, connectors) for Axelera in-house hardware products, leveraging proximity to the Taiwan supply chain and key component manufacturers. • Evaluate pin-compatible or functionally equivalent alternatives proposed during BOM reviews or component end-of-life transitions; provide electrical characterisation data and board-level validation results to the AIS design team. • Support design verification activities for new PCB revisions or new product introductions: perform bring-up, functional testing, and regression against previous hardware baselines. • Act as the local technical interface with design partners or EMS providers during engineering prototype builds (EVT/DVT), collecting build feedback and coordinating issue resolution with Axelera HW engineers. • Document qualification outcomes, test reports, and design deviation assessments in Axelera’s PLM/document control system.

Role Description We're looking for a Software Technical PM to own the day-to-day planning, execution management, and coordination of complex software development projects at Axelera AI. This is a hands-on execution management role, responsible for: - End-to-end execution management of assigned complex software projects from planning through delivery, working across multiple software sub-teams simultaneously. - Building and maintaining detailed project plans at the task and dependency level, working directly with engineering sub-team leads to establish realistic estimates, identify dependencies, and define integration milestones. - Driving the planning and coordination of the integration process for assigned projects. - Ensuring explicit definition-of-done criteria are established for each project phase. - Running daily or appropriate-cadence coordination standups for assigned projects. - Tracking estimation accuracy and delivery predictability at the task level. - Identifying single-person critical path dependencies and escalating to engineering leads. - Preparing and maintaining project-level status views, risk registers, and decision logs. - Contributing to programme-level process improvements based on lessons learned from project execution. - Working with the Software Program Manager to ensure assigned project plans are aligned with the overall release roadmap. Qualifications - 3-5 years of experience in technical programme or project management within a software-intensive technology organisation. - Demonstrated experience coordinating cross-team software integration efforts. - Sufficient technical literacy to navigate discussions about compiler toolchains, runtime systems, model optimisation, and inference pipelines. - Track record of improving delivery predictability on complex software projects. - Experience working in a matrixed environment, managing by influence across teams. - Familiarity with AI/ML model deployment pipelines is a significant advantage. - Familiarity with agile or SAFe-inspired planning methodologies. - Outstanding verbal and written communication skills in English. - Strong attention to detail, particularly in tracking task-level dependencies. - Ability to work independently with a high degree of autonomy in a fast-paced environment. Requirements - Experience in semiconductor toolchains, compilers, AI/ML frameworks, or embedded systems software. - Ability to build trust with senior engineers and drive accountability through transparency. Benefits - Attractive compensation package, including a pension plan and extensive employee insurances. - Option to get company shares. - Open culture that supports creativity and continual innovation. - Collaborative ownership and freedom with responsibility. - Commitment to cultivating a warm and inclusive environment that empowers and celebrates diversity.

• Senior primary technical contact for EMEA customers, engaging from engineers to senior leadership • Lead hardware bring-up, board integration, and embedded system debugging on-site and remotely • Support chip-down design, custom carrier board development, and embedded Linux integration • Guide customers deploying AI models and inference pipelines via the Voyager SDK • Debug PCIe, power sequencing, signal integrity, thermal, and BSP bring-up issues • Drive pre-sales engagement and design wins across OEM/ODM, integrators, and end users across Europe. • Build FAE processes, documentation, and support infrastructure for the EMEA region • Recruit, mentor, and manage EMEA FAE engineers as the team scales • Align priorities with commercial goals; contribute to EMEA and global FAE strategy • Act as the senior technical bridge between EMEA customer needs and global R&D and Product teams • Surface customer feedback and roadmap input to Product Management and R&D • Maintain relationships with key accounts, distributors, and channel partners across EMEA • Partner with Sales and BD on product introductions, onboarding, and competitive intelligence • Represent Axelera AI at EMEA industry events, conferences, and technical forums

• Register your interest in opportunities with Axelera AI after the IKOM Start-up 2026 event in Munich • Be contacted by the company if your profile aligns with future opportunities

• Senior primary technical contact for Taiwan customers, engaging from engineers to senior leadership • Lead hardware bring-up, board integration, and embedded system debugging on-site and remotely • Support chip-down design, custom carrier board development, and embedded Linux integration • Guide customers deploying AI models and inference pipelines via the Voyager SDK • Debug PCIe, power sequencing, signal integrity, thermal, and BSP bring-up issues • Drive pre-sales engagement and design wins across OEM/ODM, integrators, and end users • Build FAE processes, documentation, and support infrastructure for the Taiwan region • Recruit, mentor, and manage APAC FAE engineers as the team scales • Align priorities with commercial goals; contribute to APAC and global FAE strategy • Surface customer feedback and roadmap input to Product Management and R&D • Maintain relationships with key accounts, distributors, and channel partners in Taiwan • Partner with Sales and BD on product introductions, onboarding, and competitive intelligence

Role Description We are looking for an entrepreneurial, technically exceptional engineering leader to establish and run Axelera’s AI Enterprise Division within the AI Integrated Systems (AIS) group. This is a new function, created to take our next-generation accelerator silicon into datacenter-class form factors from PCIe accelerator cards and OAM-class modules to full 1U/2U rack systems and dense compute nodes targeting enterprise AI, sovereign cloud and HPC customers. You will build the team, shape the technical roadmap, and own end-to-end delivery of board- and system-level products for two strategic programmes. You will partner closely with the engineering leadership of the Embedded AI product line within AIS, the silicon organisation, the Voyager SDK/software group, and Axelera’s go-to-market teams serving hyperscalers, sovereign AI initiatives and the European HPC ecosystem. This role is deeply hands-on. You will review schematics and layouts, challenge power and thermal budgets, shape the BMC and platform-firmware stack, and walk the lab floor during bring-up. Strategic leadership without technical depth will not work here. Key responsibilities: - Build the Enterprise AI Server engineering team from the ground up: hire, structure and mentor a multidisciplinary organisation covering hardware architecture, PCB design, power/thermal/mechanical engineering, firmware and platform validation with in-house and 3rd party resources. - Define the technical roadmap for the division’s board- and system-level server products—PCIe Gen5/CXL accelerator cards, OAM-class modules, and full 1U/2U rack systems—aligned with the next-generation silicon roadmap. - Serve as the technical authority across architecture, schematics, PCB stack-ups, high-speed signalling (PCIe Gen5/6, CXL, high-speed SerDes), enterprise memory, power delivery and VRM design, SI/PI methodology, and mechanical/thermal integration. - Own end-to-end execution from concept through design reviews, bring-up, validation, reliability qualification, DFM/DFT/DFR and mass-production readiness, including NPI and ramp with tier-1 CMs and ODMs. - Drive datacenter-grade platform engineering: BMC-based management, Redfish/IPMI, UEFI/BIOS firmware, secure boot and root-of-trust, platform firmware resilience, enterprise RAS features, and out-of-band telemetry. - Lead the thermal and mechanical strategy for high-power accelerator platforms, including air-cooled rack designs and, where appropriate, direct liquid cooling (DLC) and immersion-ready variants. - Ensure compliance with enterprise and datacenter standards: EN 55032/35 Class A, UL 62368, EN 50600 and NEBS where applicable, alongside OCP contribution/consumption where strategic for the division. - Partner with the Embedded AI engineering leadership within AIS to align board- and system-level execution across the two product lines, sharing reference designs, validation assets and CM/ODM relationships wherever it accelerates both streams. - Co-define platform requirements with the silicon, SDK and software teams, memory topology, interconnect fabric, power states, telemetry, so that the server products showcase the accelerator’s capabilities at rack and cluster scale. - Engage directly with strategic customers, system integrators and ecosystem partners (hyperscalers, sovereign cloud operators, HPC centres, OEMs/ODMs) to shape requirements and win design-ins. - Define and enforce engineering processes, documentation standards, validation methodologies and quality gates for the new division, mapped to Axelera’s NPD framework. - Identify and mitigate technical risks, resolve engineering escalations, and drive debugging and root-cause analysis during development, qualification and early production. - Own the division’s engineering budget, CAPEX, external engineering spend and vendor relationships. Qualifications - 15+ years in hardware engineering for complex electronics products, with at least 5 years in senior leadership roles running multidisciplinary teams. - Proven track record of shipping datacenter- or server-class compute hardware into volume production: accelerator cards, GPU/xPU-class modules, server motherboards, compute nodes or rack-level systems. - Deep expertise in high-speed interfaces (PCIe Gen4/5/6, CXL, high-speed SerDes), enterprise memory, high-current power delivery and VRM design, and high-density PCB layout with rigorous SI/PI methodology. - Experience with BMC-based platform management, Redfish/IPMI, UEFI/BIOS or equivalent firmware stacks, secure boot/root-of-trust, and enterprise RAS features. - Working knowledge of datacenter thermal and mechanical design: air-cooled 1U/2U chassis, direct liquid cooling and/or immersion-ready platforms, and rack power delivery at 12V, 48V and OCP power-shelf level. - Familiarity with datacenter and enterprise compliance (EN 55032/35 Class A, UL 62368, EN 50600, NEBS where relevant) and with OCP standards and contribution/consumption processes. - Experience working with tier-1 CMs/ODMs on server-class products, including DFM, MP transfer, yield ramp and sustaining engineering. - Hands-on ability to review schematics, layouts, simulation results and lab validation data, and to make the call when the team is stuck. - Strong strategic thinker, excellent communicator, skilled at decision-making in fast-moving environments, comfortable engaging at C-level with customers and partners. Requirements - Experience building or significantly scaling an engineering team is strongly preferred. - Experience with AI accelerator platforms, GPUs or custom silicon in a datacenter context is a strong plus. - Exposure to sovereign AI, EuroHPC, HPC or European defence/dual-use datacenter programmes is a plus. - Fluent English required; additional European language is a plus. Benefits - Attractive compensation package, including a pension plan, extensive employee insurances and the option to get company shares. - An open culture that supports creativity and continual innovation. - Collaborative ownership and freedom with responsibility is characteristic for the way we act and work as a team. - Commitment to cultivating a warm and inclusive environment that empowers and celebrates every member of our team.

About Us Axelera AI is not your regular deep-tech startup. We are creating the next-generation AI platform to support anyone who wants to help advancing humanity and improve the world around us. In just four years, we have raised a total of $370 million and have built a world-class team of 220+ employees (including 49+ PhDs with more than 40,000 citations), both remotely from 18 different countries and with offices in Belgium, France, Switzerland, Italy, the UK, headquartered at the High Tech Campus in Eindhoven, Netherlands. We have also launched our Metis™ AI Platform, which achieves a 3-5x increase in efficiency and performance, and have visibility into a strong business pipeline exceeding $100 million. Our unwavering commitment to innovation has firmly established us as a global industry pioneer. Are you up for the challenge? Position Overview As Quality Manager, you will own the end-to-end quality function within Operations - from incoming components and supplier qualification, through NPI and production phases, to field returns and RMA. You will report directly to the VP of Operations and work closely with AIIS (AI Infrastructure & Integration Solutions), Product, and Engineering teams to establish robust quality systems that scale with Axelera AI's rapid growth. This is a hands-on, foundational role: you will build processes, drive cross-functional alignment, and be the primary quality authority within the Operations organisation. Key responsibilities: Hardware Product Quality (IQC / OQC / RMA) - Own and continuously improve IQC and OQC processes across all product families (M.2, PCIe, SBC). - Define acceptance criteria, inspection sampling plans, and test coverage requirements in collaboration with Engineering. - Manage the RMA process end-to-end: triaging field returns, root cause analysis (RCA), corrective action (CAPA), and reporting back to customers and internal stakeholders. - Maintain quality metrics dashboards (yield, defect rate, RMA rate) and present regular reports to Operations leadership. Supplier Quality Management (SQE / SQA) - Qualify new suppliers and ODM/CM partners (including audits, PPAP/APQP where applicable) and maintain supplier quality scorecards. - Lead supplier non-conformance (NCR) processes: issuance, follow-up, and verification of 8D/CAPA responses. - Work with procurement to drive supplier quality improvement programs for critical components (e.g., memory, power regulators, SoCs). - Support second-source qualification activities from a quality standpoint. Manufacturing / NPI Process Quality (DVT / PVT / MP) - Embed quality gates into the NPI process: define DVT/PVT exit criteria, manage DFM/DFT feedback loops with Engineering and ODMs. - Drive yield learning during NPI phases and ensure smooth quality handover from NPI to mass production. - Maintain and govern process control documents (control plans, FMEAs, work instructions) in collaboration with CM/ODM partners. Product Certifications & Compliance - Maintain and manage product regulatory certifications (CE, FCC, UL, and equivalent) across all product families, ensuring ongoing compliance throughout the product lifecycle. - Coordinate with NPI and design teams during certification obtainment phases to ensure quality inputs and documentation are in place; own the certification maintenance and renewal process post-MP. - Serve as the internal point of contact for regulatory compliance queries related to product quality (RoHS, REACH, WEEE) in coordination with Legal and Product teams. - Establish and maintain the Operations quality management system (QMS), aligned with ISO 9001 or equivalent frameworks. - Drive root cause analysis culture across Operations using structured methodologies (8D, Ishikawa, 5-Why). - Ensure quality documentation is audit-ready and compliant with customer and regulatory requirements. Qualifications: Must Have - 7+ years of experience in hardware/electronics quality management, with direct experience in IQC, OQC, and supplier quality. - Background in semiconductor, chip-level, or system integration environments (e.g., SoC/module bring-up, board-level integration, or hardware platform development). - Hands-on experience managing ODM/CM relationships and conducting supplier audits. - Proficiency with structured quality methodologies: 8D, FMEA, CAPA, SPC, control plans. - Experience supporting NPI quality gates (DVT/PVT) and transitioning products to mass production. - Strong analytical skills - comfortable working with data to drive quality decisions. - Excellent communication skills in English; ability to work across global, cross-functional teams. Nice to Have - Experience in AI/ML hardware, PCIe/M.2 form-factor products, or AI SBCs. - ISO 9001 Lead Auditor certification or equivalent QMS qualification. - Experience working in a scale-up or early-stage hardware company. Location We offer a flexible working arrangement, with options to: - Work from one of our Axelera AI offices (Florence and Milan in Italy, Amsterdam and Eindhoven in the Netherlands, Leuven in Belgium, Paris in France, Zurich in Switzerland, or Bristol in the United Kingdom) if you're already based in the vicinity. - Work fully remotely from any European country (incl. the UK) you are already in. - Relocate with us and work from Amsterdam or Eindhoven in the Netherlands What we offer  This is your chance to shape and be part of a dynamic, fast-growing, international organization. We offer an attractive compensation package, including a pension plan, extensive employee insurances and the option to get company shares.  An open culture that supports creativity and continual innovation is awaiting you. Collaborative ownership and freedom with responsibility is characteristic for the way we act and work as a team.  At Axelera AI, we wholeheartedly embrace equal opportunity and hold diversity in the highest regard. Our steadfast commitment is to cultivate a warm and inclusive environment that empowers and celebrates every member of our team. We welcome applicants from all backgrounds to join us in shaping the future of AI.