Five Years Out
Design Verification Engineer
Location
Texas + 1 moreAll locations: Texas | California
Posted
45 days ago
Salary
0
Seniority
Mid Level
Job Description
Design Verification Engineer
Arrow Electronics
Role Description The Design Verification Engineer will be responsible for the following: - At least 6+ years of experience in System Verilog HVL and C++/C - At least 6+ years of experience in UVM - Experience in complete verification cycle which includes: - Development of test plan - BFM/Driver/Monitor/Scoreboard component development and integration in test bench - Stress/corner testing - Failure debug - Gate level simulations - Assertions and coverage closure - Proficient in SVTB/UVM, C++ testbench - Understanding of DSP is a plus - Experience with Subversion for Repository and Bugzilla is also a plus - Proficient in debug and assertions coding - Verification closure with team Qualifications - At least 6+ years of experience in System Verilog HVL and C++/C - At least 6+ years of experience in UVM - Experience with Make/Perl/Python or any scripting language - Any protocol experience is fine - Ensure customer satisfaction - Reporting to customer on daily or weekly progress effectively Requirements - Fully On-Site: Must be able to travel to an Arrow Client office location as requested by Arrow Client leadership - Location: Austin, Texas (Preferred) / Can be considered remote Benefits - Medical, Dental, Vision Insurance - 401k, With Matching Contributions - Short-Term/Long-Term Disability Insurance - Health Savings Account (HSA)/Health Reimbursement Account (HRA) Options - Paid Time Off - Tuition Reimbursement - Growth Opportunities - And more!
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