FPGA Emulation Engineer
Location
Iowa
Posted
10 days ago
Salary
$150K - $180K / year
Seniority
Senior
Job Description
FPGA Emulation Engineer
Quest Defense
• Build and maintain FPGA emulation environments using Siemens Veloce or similar platforms • Port and optimize RTL and test environments from simulation into emulation • Debug complex system-level issues that only appear at scale or in hardware-accelerated environments • Improve emulation performance, compile times, and runtime efficiency • Integrate UVM-based environments into emulation workflows (not building UVM from scratch, but making it work in emulation) • Support validation of high-speed interfaces and system-level data flows • Collaborate with RTL, verification, and systems teams to resolve design and integration issues • Enable full-chip and subsystem validation that cannot be achieved in simulation alone • Support DO-254 verification activities, including traceability and test evidence where needed • Help define best practices for emulation workflows across programs
Job Requirements
- 5+ years of experience in FPGA/ASIC verification or validation
- Hands-on experience with hardware emulation platforms (Siemens Veloce, Cadence Palladium, Synopsys ZeBu, etc.)
- Experience bringing up designs in emulation environments and debugging system-level issues
- Strong understanding of RTL design and verification workflows
- Experience bridging simulation ↔ emulation environments
- Ability to analyze performance bottlenecks and optimize emulation runs
- Familiarity with SystemVerilog and UVM (integration level, not pure architect focus)
- Experience debugging interfaces, data paths, and timing-related issues
- Ability to work across teams and drive technical solutions
Benefits
- Competitive pay
- Comprehensive medical/dental/life and disability coverage
- 401(k) with employer match
- Professional development support
- Flexible, friendly workplace
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