Cincinnatus is an enterprise staffing company that partners with leading technology companies to source and employ highly skilled professionals for full-time and long-term contingent roles. Cincinnatus serves as the employer of record for these engagements, providing W-2 employment, payroll, benefits, and compliance, while placing employees directly within client teams to work on high-impact initiatives. Roles hired through Cincinnatus are not project-based or freelance engagements. They are structured, role-based positions that typically involve full-time or fixed-term commitments, close collaboration with a client's internal teams, and integration into standard enterprise workflows. Cincinnatus is a legal entity separate from Mercor. While opportunities may be discovered through Mercor's platform, employment, onboarding, payroll, and benefits for these roles are administered by Cincinnatus. Equal Employment Opportunity Cincinnatus is proud to be an Equal Employment Opportunity employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, reproductive health decisions, or related medical conditions), sexual orientation, gender identity, gender expression, age, status as a protected veteran, status as an individual with a disability, genetic information, political views or activity, or any other legally protected characteristic. Cincinnatus is committed to providing reasonable accommodations for qualified individuals with disabilities and disabled veterans throughout the job application process.
Senior Design Verification Engineer
Location
Worldwide
Posted
31 days ago
Salary
$100 - $175 / hour
Seniority
Senior
Job Description
Senior Design Verification Engineer
Mercor
Role Description Mercor connects elite creative and technical talent with leading AI research labs. We are looking for RTL Design Engineers for a contract position. - Evaluate and enhance AI model training for digital chip design and verification. - Design and implement RTL components using Verilog/SystemVerilog. - Develop and maintain ASIC design flows including lint, synthesis, and timing analysis. - Collaborate with architecture, verification, and implementation teams to ensure seamless integration. - Utilize EDA tools for simulation, waveform debug, and coverage analysis. - Work independently and asynchronously to meet project deadlines and improve AI model performance. Qualifications - 3–10 years of experience in digital RTL design or design verification. - Strong proficiency in Verilog/SystemVerilog and UVM. - Solid understanding of digital design fundamentals: FSMs, datapaths, pipelines, FIFOs, arbiters, clock/reset domains, bus protocols. - Experience with ASIC design flows and EDA tools. - Familiarity with leveraging LLM-based tools for chip design and verification workflows. Requirements - Knowledge of AMBA protocols (AXI, AHB, APB). - Background in CPU, GPU/ML accelerator, networking, memory subsystem, PCIe/high-speed IO, SoC interconnect, low-power design. - Exposure to formal verification or SV/UVM-based design verification. Benefits - Compensation: $100–$175/hour - Location: Remote - Duration: 3+ months - Commitment: 40 hours/week Application Process - Upload resume - AI interview based on your resume - Submit form Start Date: Week of 04/23; applications reviewed on a rolling basis. For details about the interview process and platform information, please check: Interview Process For any help or support, reach out to: support@mercor.com
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