Role Description The position focuses on functional verification of advanced digital designs used in high‑performance AI accelerator products for the cybersecurity and data‑center market. The engineer will take ownership of verification activities for complex ASIC/SoC components, working closely with architecture, RTL, and software teams. This is a senior‑level role designed for specialists who want to work on cutting‑edge hardware in a rapidly growing deep‑tech environment. Key Responsibilities - Develop and execute verification plans based on architecture and RTL specifications. - Build, extend, and maintain UVM‑based verification environments, including agents, drivers, sequencers, monitors, scoreboards, and checkers. - Implement constrained‑random and coverage‑driven verification methodologies. - Debug complex hardware and hardware/software interactions using industry‑standard tools. - Collaborate with RTL designers, architects, and validation teams to identify issues and drive them to closure. - Analyze functional coverage, identify gaps, and ensure verification completeness. - Participate in subsystem and SoC‑level integration and verification activities. Qualifications - B.Sc or M.Sc in Electrical Engineering, Computer Engineering, or a related field. - Minimum 5 years of hands‑on experience in ASIC/SoC verification. - Strong proficiency in SystemVerilog, UVM, and constrained‑random verification. - Solid understanding of digital design principles and RTL coding (Verilog/VHDL). - Experience with EDA simulation and debug tools from Synopsys, Cadence, or Siemens/Mentor. - Proven ability to debug complex digital logic and HW/SW interactions. - Strong analytical mindset, communication skills, and ability to work in multidisciplinary teams. Preferred Qualifications - Experience with high‑speed interfaces, memory subsystems, or AI/ML accelerators. - Familiarity with protocols such as AXI, PCIe, DDR, or CXL. - Experience building UVM environments from scratch. Benefits - Equity participation with long‑term upside potential. - Full‑time employment contract. - Work alongside top global experts in a highly specialized domain not commonly found in Poland. - Opportunity to join a fast‑growing deep‑tech company building unique AI hardware products. - Competitive compensation and long‑term career growth within a stable, well‑funded organization.

• Flock Safety is looking for a Firmware Engineer to join our Device Firmware Team. • Responsible for all of the code running on thousands of solar-powered devices that are at the heart of our mission. • Focus on developing high-quality MCU firmware for existing and next-generation platforms. • Work with key internal stakeholders and external vendors to ensure deliverables meet our development and design bar. • Develop customizations in the drivers and collaborate cross-functionally to deliver quality software and firmware.

DFT Engineer (Senior / Staff) At Niobium Microsystems, we develop high performance microelectronic products to enable the secure collection, processing, and distribution of critical data. We are a trusted partner for DoD and commercial customers whose solutions require lower power, higher efficiency, and proven security. Founded as a 2021 spinout from a world-class security and computing systems R&D company, our team combines decades of experience in advanced semiconductor design with experience in advanced cryptography. Niobium is headquartered in Dayton, Ohio with additional locations in Portland, Oregon; and Columbus, Ohio. We will not be limited by geography for the right candidate. POSITION DESCRIPTION / Niobium Microsystems is seeking a Senior / Staff DFT Engineer with 8+ years of relevant industry experience. This role will serve as a technical lead responsible for defining and executing Design-for-Test (DFT) strategy across complex SoC designs. As a DFT Engineer, you will own the full test insertion flow from early architecture through post-silicon validation. You will collaborate closely with RTL, physical design, and test engineering teams to ensure high fault coverage, manufacturability, and first-pass silicon success. JOB RESPONSIBILITIES / Primary Responsibilities: - Overview - Own and drive end-to-end DFT strategy for complex SoCs, from architecture through silicon bring-up - Serve as DFT lead for major subsystems or full-chip execution - DFT Architecture & Planning - Define and implement DFT architecture including scan, compression, and MBIS - Establish DFT insertion strategies at RTL and/or netlist stages - Implementation & Integration - Drive scan chain stitching, compression insertion, and clock/reset domain handling - Integrate DFT features across subsystems including SRAM, register files, and mixed-signal blocks - Collaborate with physical design to meet timing, routing, and signoff requirements - Verification & Coverage Closure - Execute ATPG and fault simulation to achieve high fault coverage targets - Develop and validate test patterns for scan, BIST, and low-power modes - Track and drive DFT sign off criteria including coverage, waivers, and escape analysis - ATE & Post-Silicon Bring-Up - Partner with test engineering to translate patterns to ATE platforms - Support silicon bring-up, debug failing patterns, and perform yield analysis - Conduct shmoo analysis and root-cause failures - Leadership & Methodology - Drive DFT methodology improvements, automation, and flow optimization - Develop scripts and infrastructure for scalable DFT flows - Represent DFT in cross-functional reviews and program milestones DESIRED SKILLS & EXPERIENCE / - Required Experience - B.S. or M.S. in Electrical Engineering, Computer Engineering, or related field - 8+ years of hands-on DFT experience in ASIC or SoC design - Strong expertise in scan architecture, ATPG, compression techniques, and MBIST - Experience driving DFT from RTL through GDSII, including physical design collaboration - Hands-on experience with ATE bring-up and post-silicon debug - Proficiency in scripting (Tcl, Python) for automation and flow development - Technical Experience - DFT tools such as Siemens Tessent, Synopsys TestMAX, or equivalent - Familiarity with RTL design and simulation tools (Verilog/SystemVerilog, VCS, Xcelium) - Experience with large-scale SoC integration and multi-clock/multi-power domains - Strong understanding of DFT timing, physical constraints, and signoff requirements - Experience working with ATE platforms such as Advantest or Teradyne is a plus BENEFITS / - Competitive salaries - Employer paid health care - Employer contribution to health savings account - Flexible time off - Flexible work location with remote options - Location Preferences: Portland, OR;Columbus, OH; Dayton, OH; Fayetteville, AR; or San Francisco, CA - 401K employer match CONTACT / careers@niobiummicrosystems.com 444 E 2nd Street, Suite 250, Dayton, OH 45402 niobiummicrosystems.com Location Remote (Remote) Department Engineering Employment Type Full-Time Minimum Experience Mid-level

Role Description We’re looking for a HPC GPU Pipeline Mechanic with familiarity in writing and maintaining optimised software for a variety of platforms, to help customers bring their GPU workloads to our HPC infrastructure. As a HPC GPU Pipeline Mechanic you’ll be part of a team of technical experts responsible for ensuring that customers can use our compute infrastructure as productively as possible. - Ongoing maintenance of scientific applications on EngineRoom.io's Private Cloud HPC environment - Inspection and maintenance of software written by other members of the team - Achieving a basic understanding of our customers' scientific domains - Acting as 3rd-level technical support for otherwise-unresolvable customer issues - Providing and receiving regular, constructive feedback to and from your peers - Collaborating on priority and scheduling for rapid project delivery Qualifications - Strong C/C++ skills, along with at least one GPU-targeted toolchain (ideally CUDA) - Experience using GP/GPUs for numerical processing in a commercial or academic setting - Understanding of Kubernetes, Clusters, and K8 Administration - Excellent written and spoken business and technical English, suitable for working directly with clients - Impeccable professional references Requirements - Significant expertise as a Linux user/administrator - Experience optimising for both NVIDIA and AMD GPUs, Graphcore, and Intel IPUs and x86 CPUs - A background or interest in some branch of science - Sufficient maths to be able to implement algorithms described in scientific papers Benefits - Choice of technical or organizational leadership career growth - State-of-the-art technology environment - Innovation, proof-of-concept, and first-article rapid prototype focus - Small-team workplace flexibility and work-life balance - Start-up and innovation culture