• Flock Safety is looking for a Firmware Engineer to join our Device Firmware Team. • Responsible for all of the code running on thousands of solar-powered devices that are at the heart of our mission. • Focus on developing high-quality MCU firmware for existing and next-generation platforms. • Work with key internal stakeholders and external vendors to ensure deliverables meet our development and design bar. • Develop customizations in the drivers and collaborate cross-functionally to deliver quality software and firmware.

DFT Engineer (Senior / Staff) At Niobium Microsystems, we develop high performance microelectronic products to enable the secure collection, processing, and distribution of critical data. We are a trusted partner for DoD and commercial customers whose solutions require lower power, higher efficiency, and proven security. Founded as a 2021 spinout from a world-class security and computing systems R&D company, our team combines decades of experience in advanced semiconductor design with experience in advanced cryptography. Niobium is headquartered in Dayton, Ohio with additional locations in Portland, Oregon; and Columbus, Ohio. We will not be limited by geography for the right candidate. POSITION DESCRIPTION / Niobium Microsystems is seeking a Senior / Staff DFT Engineer with 8+ years of relevant industry experience. This role will serve as a technical lead responsible for defining and executing Design-for-Test (DFT) strategy across complex SoC designs. As a DFT Engineer, you will own the full test insertion flow from early architecture through post-silicon validation. You will collaborate closely with RTL, physical design, and test engineering teams to ensure high fault coverage, manufacturability, and first-pass silicon success. JOB RESPONSIBILITIES / Primary Responsibilities: - Overview - Own and drive end-to-end DFT strategy for complex SoCs, from architecture through silicon bring-up - Serve as DFT lead for major subsystems or full-chip execution - DFT Architecture & Planning - Define and implement DFT architecture including scan, compression, and MBIS - Establish DFT insertion strategies at RTL and/or netlist stages - Implementation & Integration - Drive scan chain stitching, compression insertion, and clock/reset domain handling - Integrate DFT features across subsystems including SRAM, register files, and mixed-signal blocks - Collaborate with physical design to meet timing, routing, and signoff requirements - Verification & Coverage Closure - Execute ATPG and fault simulation to achieve high fault coverage targets - Develop and validate test patterns for scan, BIST, and low-power modes - Track and drive DFT sign off criteria including coverage, waivers, and escape analysis - ATE & Post-Silicon Bring-Up - Partner with test engineering to translate patterns to ATE platforms - Support silicon bring-up, debug failing patterns, and perform yield analysis - Conduct shmoo analysis and root-cause failures - Leadership & Methodology - Drive DFT methodology improvements, automation, and flow optimization - Develop scripts and infrastructure for scalable DFT flows - Represent DFT in cross-functional reviews and program milestones DESIRED SKILLS & EXPERIENCE / - Required Experience - B.S. or M.S. in Electrical Engineering, Computer Engineering, or related field - 8+ years of hands-on DFT experience in ASIC or SoC design - Strong expertise in scan architecture, ATPG, compression techniques, and MBIST - Experience driving DFT from RTL through GDSII, including physical design collaboration - Hands-on experience with ATE bring-up and post-silicon debug - Proficiency in scripting (Tcl, Python) for automation and flow development - Technical Experience - DFT tools such as Siemens Tessent, Synopsys TestMAX, or equivalent - Familiarity with RTL design and simulation tools (Verilog/SystemVerilog, VCS, Xcelium) - Experience with large-scale SoC integration and multi-clock/multi-power domains - Strong understanding of DFT timing, physical constraints, and signoff requirements - Experience working with ATE platforms such as Advantest or Teradyne is a plus BENEFITS / - Competitive salaries - Employer paid health care - Employer contribution to health savings account - Flexible time off - Flexible work location with remote options - Location Preferences: Portland, OR;Columbus, OH; Dayton, OH; Fayetteville, AR; or San Francisco, CA - 401K employer match CONTACT / careers@niobiummicrosystems.com 444 E 2nd Street, Suite 250, Dayton, OH 45402 niobiummicrosystems.com Location Remote (Remote) Department Engineering Employment Type Full-Time Minimum Experience Mid-level

Role Description We’re looking for a HPC GPU Pipeline Mechanic with familiarity in writing and maintaining optimised software for a variety of platforms, to help customers bring their GPU workloads to our HPC infrastructure. As a HPC GPU Pipeline Mechanic you’ll be part of a team of technical experts responsible for ensuring that customers can use our compute infrastructure as productively as possible. - Ongoing maintenance of scientific applications on EngineRoom.io's Private Cloud HPC environment - Inspection and maintenance of software written by other members of the team - Achieving a basic understanding of our customers' scientific domains - Acting as 3rd-level technical support for otherwise-unresolvable customer issues - Providing and receiving regular, constructive feedback to and from your peers - Collaborating on priority and scheduling for rapid project delivery Qualifications - Strong C/C++ skills, along with at least one GPU-targeted toolchain (ideally CUDA) - Experience using GP/GPUs for numerical processing in a commercial or academic setting - Understanding of Kubernetes, Clusters, and K8 Administration - Excellent written and spoken business and technical English, suitable for working directly with clients - Impeccable professional references Requirements - Significant expertise as a Linux user/administrator - Experience optimising for both NVIDIA and AMD GPUs, Graphcore, and Intel IPUs and x86 CPUs - A background or interest in some branch of science - Sufficient maths to be able to implement algorithms described in scientific papers Benefits - Choice of technical or organizational leadership career growth - State-of-the-art technology environment - Innovation, proof-of-concept, and first-article rapid prototype focus - Small-team workplace flexibility and work-life balance - Start-up and innovation culture

DFT Verification Engineer Who we are: We are a stealth-mode startup building foundational technology to address performance, scalability, and resiliency challenges in large-scale AI data center clusters. We are backed by top-tier VC firms and notable angel investors. The company is led by experienced builders and operators who have founded companies, taken them to scale, and exited successfully. We work with a strong sense of unity and shared responsibility, and we expect trust, integrity, and respect in how we collaborate and make decisions. We hold ourselves accountable to one another and to the quality of the work we deliver. Headquartered in Silicon Valley, we operate across a mix of remote and on-site locations in the U.S. and Canada. We aim to create an environment where people are treated fairly, supported in their growth, and are empowered to do meaningful work alongside others who take the craft seriously. What we need: An experienced DFT Verification Engineer responsible for ensuring the functionality, correctness, and quality of ASIC DFT logic. This role focuses on building robust verification environments, executing coverage-driven verification plans, and working closely with DFT design engineers and manufacturing engineers to deliver reliable, high-quality silicon. The ideal candidate has deep hands-on experience with SystemVerilog, UVM (or similar methodologies), and modern verification workflows, and is comfortable driving verification efforts from planning through closure. The ideal candidate is also knowledgeable about DFT topics such as scan/ATPG, JTAG, ijtag (ICL/PDL), boundary scan, MBIST, memory repair, and fuseboxes. Should have experience with gate-level simulation and tester pattern formats such as STIL. Key Responsibilities: - Develop, implement, and maintain RTL verification environments using UVM or equivalent methodologies - Create and execute coverage-driven verification plans aligned with design specifications - Use EDA DFT tools (e.g., TestMax, Tessent) to create and run recommended pre-silicon test cases for MBIST and scan fabric inserted by those tools - Develop directed test cases for other (non-vendor-supplied) DFT logic to validate functionality and identify corner cases - Assist in verifying ATPG patterns, especially at SOC level, along with manufacturing reset sequences - Analyze simulation results, debug complex verification and design issues, and perform root-cause analysis in collaboration with DFT design engineers - Implement and track functional and code coverage, driving verification to closure - Develop reusable verification components and write SystemVerilog Assertions (SVA) - Participate in design and verification reviews, providing input on design testability, correctness, and optimization - Automate regression testing and enhance verification infrastructure using Python and scripting - Contribute to continuous improvement of verification processes, tools, and methodologies - Along with the DFT designers, help support post-silicon test bring-up debug Required Skills and Qualifications: - Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field - 5+ years of experience in digital design verification, with at least 2 in DFT verification specifically - Strong hands-on experience with UVM-based or similar verification methodologies - Proficiency in SystemVerilog - Experience in scripting (preferably Python) and automation - Experience with industry-standard EDA tools (e.g., Synopsys VCS, Siemens/Mentor Questa, Cadence Xcelium) - Experience with industry-standard EDA DFT tools (e.g., Synopsys TestMax + Yield Accelerator, Siemens Tessent) - Solid understanding of digital design fundamentals - Experience with verification of test sequences for high-speed PHY logic including PCIe and Ethernet (10G/40G/100G) - Strong analytical and problem-solving skills - Clear written and verbal communication skills for cross-functional collaboration - High attention to detail and ability to deliver reliable, high-quality verification outcomes - Ability to work independently and manage tasks to completion Desired Skills: - Experience with change control systems, especially git - Experience verifying SoC-level designs Compensation: Target base salary for this role is $160,000 – $220,000 per year, plus meaningful equity, benefits, and 401(k). Salary ranges are determined by role, level, experience, and location.