Delos Data Inc

DFT Verification Engineer Who we are: We are a stealth-mode startup building foundational technology to address performance, scalability, and resiliency challenges in large-scale AI data center clusters. We are backed by top-tier VC firms and notable angel investors. The company is led by experienced builders and operators who have founded companies, taken them to scale, and exited successfully. We work with a strong sense of unity and shared responsibility, and we expect trust, integrity, and respect in how we collaborate and make decisions. We hold ourselves accountable to one another and to the quality of the work we deliver. Headquartered in Silicon Valley, we operate across a mix of remote and on-site locations in the U.S. and Canada. We aim to create an environment where people are treated fairly, supported in their growth, and are empowered to do meaningful work alongside others who take the craft seriously. What we need: An experienced DFT Verification Engineer responsible for ensuring the functionality, correctness, and quality of ASIC DFT logic. This role focuses on building robust verification environments, executing coverage-driven verification plans, and working closely with DFT design engineers and manufacturing engineers to deliver reliable, high-quality silicon. The ideal candidate has deep hands-on experience with SystemVerilog, UVM (or similar methodologies), and modern verification workflows, and is comfortable driving verification efforts from planning through closure. The ideal candidate is also knowledgeable about DFT topics such as scan/ATPG, JTAG, ijtag (ICL/PDL), boundary scan, MBIST, memory repair, and fuseboxes. Should have experience with gate-level simulation and tester pattern formats such as STIL. Key Responsibilities: - Develop, implement, and maintain RTL verification environments using UVM or equivalent methodologies - Create and execute coverage-driven verification plans aligned with design specifications - Use EDA DFT tools (e.g., TestMax, Tessent) to create and run recommended pre-silicon test cases for MBIST and scan fabric inserted by those tools - Develop directed test cases for other (non-vendor-supplied) DFT logic to validate functionality and identify corner cases - Assist in verifying ATPG patterns, especially at SOC level, along with manufacturing reset sequences - Analyze simulation results, debug complex verification and design issues, and perform root-cause analysis in collaboration with DFT design engineers - Implement and track functional and code coverage, driving verification to closure - Develop reusable verification components and write SystemVerilog Assertions (SVA) - Participate in design and verification reviews, providing input on design testability, correctness, and optimization - Automate regression testing and enhance verification infrastructure using Python and scripting - Contribute to continuous improvement of verification processes, tools, and methodologies - Along with the DFT designers, help support post-silicon test bring-up debug Required Skills and Qualifications: - Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field - 5+ years of experience in digital design verification, with at least 2 in DFT verification specifically - Strong hands-on experience with UVM-based or similar verification methodologies - Proficiency in SystemVerilog - Experience in scripting (preferably Python) and automation - Experience with industry-standard EDA tools (e.g., Synopsys VCS, Siemens/Mentor Questa, Cadence Xcelium) - Experience with industry-standard EDA DFT tools (e.g., Synopsys TestMax + Yield Accelerator, Siemens Tessent) - Solid understanding of digital design fundamentals - Experience with verification of test sequences for high-speed PHY logic including PCIe and Ethernet (10G/40G/100G) - Strong analytical and problem-solving skills - Clear written and verbal communication skills for cross-functional collaboration - High attention to detail and ability to deliver reliable, high-quality verification outcomes - Ability to work independently and manage tasks to completion Desired Skills: - Experience with change control systems, especially git - Experience verifying SoC-level designs Compensation: Target base salary for this role is $160,000 – $220,000 per year, plus meaningful equity, benefits, and 401(k). Salary ranges are determined by role, level, experience, and location.

Verification Engineer Who we are: We are a stealth-mode startup building foundational technology to address performance, scalability, and resiliency challenges in large-scale AI data center clusters. We are backed by top-tier VC firms and notable angel investors. The company is led by experienced builders and operators who have founded companies, taken them to scale, and exited successfully. We work with a strong sense of unity and shared responsibility, and we expect trust, integrity, and respect in how we collaborate and make decisions. We hold ourselves accountable to one another and to the quality of the work we deliver. Headquartered in Silicon Valley, we operate across a mix of remote and on-site locations in the U.S. and Canada. We aim to create an environment where people are treated fairly, supported in their growth, and are empowered to do meaningful work alongside others who take the craft seriously. What we need: An experienced RTL Verification Engineer responsible for ensuring the functionality, correctness, and quality of complex digital designs across ASIC and FPGA platforms. This role focuses on building robust verification environments, executing coverage-driven verification plans, and working closely with RTL design engineers to deliver reliable, high-quality silicon. The ideal candidate has deep hands-on experience with SystemVerilog, UVM (or similar methodologies), and modern verification workflows, and is comfortable driving verification efforts from planning through closure. Key Responsibilities: · Develop, implement, and maintain RTL verification environments using UVM or equivalent methodologies · Create and execute coverage-driven verification plans aligned with design specifications · Develop directed and constrained-random test cases and sequences to validate functionality and identify corner cases · Analyze simulation results, debug complex verification and design issues, and perform root-cause analysis in collaboration with RTL design engineers · Implement and track functional and code coverage, driving verification to closure · Develop reusable verification components and write SystemVerilog Assertions (SVA) · Participate in design and verification reviews, providing input on design testability, correctness, and optimization · Automate regression testing and enhance verification infrastructure using Python and scripting · Contribute to continuous improvement of verification processes, tools, and methodologies Required Skills and Qualifications: · Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field · 7+ years of experience in digital design verification · Strong hands-on experience with UVM-based or similar verification methodologies · Proficiency in SystemVerilog, UVM, and Python · Experience with industry-standard EDA tools (e.g., Synopsys VCS, Siemens/Mentor Questa, Cadence Xcelium) · Solid understanding of digital design fundamentals · Experience verifying standard bus and interconnect protocols such as AXI, AXI-S, and APB · Experience with high-speed communication protocols including PCIe, Ethernet (10G/40G/100G), SPI, and I²C · Strong analytical and problem-solving skills · Clear written and verbal communication skills for cross-functional collaboration · High attention to detail and ability to deliver reliable, high-quality verification outcomes · Ability to work independently and manage tasks to completion Desired Skills: · Experience with formal verification techniques and tools · Experience verifying processor subsystems or SoC-level designs Compensation: Target base salary for this role is $160,000 – $220,000 per year, plus meaningful equity, benefits, and 401(k). Salary ranges are determined by role, level, experience, and location. #LI-EW1

System Software Engineer - AI About us: We are a stealth-mode startup building foundational technology to address performance, scalability, and resiliency challenges in large-scale AI data center clusters. We are backed by top-tier VC firms and notable angel investors. The company is led by experienced builders and operators who have founded companies, taken them to scale, and exited successfully. We work with a strong sense of unity and shared responsibility, and we expect trust, integrity, and respect in how we collaborate and make decisions. We hold ourselves accountable to one another and to the quality of the work we deliver. Headquartered in Silicon Valley, we operate across a mix of remote and on-site locations in the U.S. and Canada. We aim to create an environment where people are treated fairly, supported in their growth, and are empowered to do meaningful work alongside others who take the craft seriously. We are looking for: We are looking for a talented System Software Engineer to help us redefine the infrastructure layer of AI. In this role, you will bridge the gap between high-level AI frameworks and low-level system software. You will be responsible for designing and implementing the communication and execution primitives that allow large-scale AI models to run efficiently across thousands of GPUs. We are looking for a "builder" who thrives in the early stages of a product’s lifecycle and is passionate about solving the "hard" systems problems of the generative AI era. Key Responsibilities: - Collaborate across the stack to influence the design of our foundational technology, ensuring it meets the needs of next-generation AI models. - Identify and resolve performance bottlenecks in distributed training and inference workloads through deep-dive analysis of the software-hardware interface. - Conduct rigorous performance benchmarking and characterization on multi-node clusters. Required Skills and Qualifications: - Strong proficiency in C++ and Python, with a deep understanding of systems programming fundamentals (memory management, concurrency, OS internals). - Proficient in a Linux development environment. Desired Skills: - Experience with GPU programming (CUDA) and performance optimization for parallel architectures. - Familiarity with distributed AI frameworks (PyTorch, JAX, or DeepSpeed) and/or inference engines (vLLM, SGLang, Dynamo/TRT-LLM). - Hands-on experience with large-scale cluster orchestration and telemetry tools. Education: - Bachelor's or Master's degree in Computer Engineering, Computer Science, or a related field. Compensation: Target base salary for this role is $140,000 - $200,000 per year + meaningful equity + benefits + 401k. Our salary ranges are determined by role, level, experience, and location. #LI-EW1

Advanced Packaging Engineer – Design & Signal Integrity Who we are: We are a stealth-mode startup building foundational technology to address performance, scalability, and resiliency challenges in large-scale AI data center clusters. We are backed by top-tier VC firms and notable angel investors. The company is led by experienced builders and operators who have founded companies, taken them to scale, and exited successfully. We work with a strong sense of unity and shared responsibility, and we expect trust, integrity, and respect in how we collaborate and make decisions. We hold ourselves accountable to one another and to the quality of the work we deliver. Headquartered in Silicon Valley, we operate across a mix of remote and on-site locations in the U.S. and Canada. We aim to create an environment where people are treated fairly, supported in their growth, and are empowered to do meaningful work alongside others who take the craft seriously. What we need: We are looking for an Electrical Engineer for ASIC Package Design & Signal Integrity to design, model, and validate advanced semiconductor packages to ensure high-speed data and power integrity, focusing on minimizing noise, reflections, and ensuring manufacturability for custom chips Key tasks include running simulations (using tools like Ansys HFSS, Cadence Sigrity, ADS), defining package specifications, collaborating with IC designers and suppliers, analyzing power delivery networks (PDN), and debugging hardware for high-speed interfaces (UCIe,Ethernet). Key Responsibilities: - Package Development: Select and design optimal multi-die IC package types considering electrical performance, cost, and manufacturability. - Signal Integrity (SI) Analysis: Perform pre- and post-layout simulations (e.g., eye diagrams, crosstalk) for high-speed interfaces (UCIe, D2D, high-speed serdes). - Power Integrity (PI) Analysis: Model and simulate Power Delivery Networks (PDN) for low-voltage, high-current supplies, including AC/DC analysis and IR drop. - Modeling & Simulation: Develop accurate simulation models (S-parameters, IBIS-AMI) for packages, PCBs, and sockets. - Cross-Functional Collaboration: Work with IC design, physical design, board layout, and marketing teams to define requirements and resolve issues. - Layout Review: Guide PCB/package layout, reviewing stack-ups, trace routing, and component placement for optimal SI/PI performance. - Lab Validation: Support hardware bring-up, debug, and correlation between simulation/models and physical measurements. - Technology Development: Research and implement new SI/PI techniques and tools for next-generation products. Required Skills and Qualifications: - B.S./M.S. in Electrical Engineering or related field. - Strong understanding of EM theory, transmission lines, and signal integrity principles. - Expertise in SI/PI simulation tools (Keysight ADS, Ansys HFSS, Cadence Sigrity/PowerSI). - Experience with high-speed interfaces (UCIe, D2D, Ethernet). - Knowledge of board materials, stack-up design, and constraint management. - Hands-on experience with lab equipment (VNA, TDR, Oscilloscope). - Proficiency in programming/automation (Python, Matlab) is a plus. - Experience in Multi-Die package designs using standard UCIe (AP and/or SP) - Experience selecting and managing sub-contractors - Experience interfacing with TSMC for packaging options (bumping) Compensation: Target base salary for this role is $160,000 - $220,000 per year + meaningful equity + benefits + 401k. Our salary ranges are determined by role, level, experience, and location. #LI-EW1

Senior FPGA Design Engineer Who we are: We are a stealth-mode startup building foundational technology to address performance, scalability, and resiliency challenges in large-scale AI data center clusters. We are backed by top-tier VC firms and notable angel investors. The company is led by experienced builders and operators who have founded companies, taken them to scale, and exited successfully. We work with a strong sense of unity and shared responsibility, and we expect trust, integrity, and respect in how we collaborate and make decisions. We hold ourselves accountable to one another and to the quality of the work we deliver. Headquartered in Silicon Valley, we operate across a mix of remote and on-site locations in the U.S. and Canada. We aim to create an environment where people are treated fairly, supported in their growth, and are empowered to do meaningful work alongside others who take the craft seriously. What we need: A Senior FPGA Design Engineer to design, develop, verify, and integrate complex digital logic systems on high-performance FPGA platforms. This role focuses on AMD/Xilinx architectures including Virtex and Versal, and spans the full FPGA development lifecycle from architecture through lab bring-up and deployment. Key Responsibilities: - Translate high-level system requirements into FPGA architectural and micro-architectural specifications - Develop robust, clean, and maintainable RTL code using VHDL, Verilog, and SystemVerilog - Create and utilize simulation testbenches using tools such as XCelium and Vivado to verify functionality and performance - Perform synthesis, place-and-route, and static timing analysis using Xilinx tools (Vivado, ISE) - Optimize designs for performance, power, and area (PPA) - Bring up FPGAs on custom PCBs and debug using oscilloscopes, logic analyzers, and on-chip debugging tools (Vivado Logic Analyzer) - Develop scripts to update and download FPGA clusters in live server environments - Collaborate with hardware, software, systems, and verification engineers to ensure system integration and validation - Create and maintain design specifications, test plans, and test results documentation - Build and maintain FPGA software environments using Vitis, including toolchains, reference drivers, and processor core environments Required Skills and Qualifications: - Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field - Proficiency with AMD/Xilinx FPGA platforms - Proficiency with Vivado, Vitis, and ISE development environments - Strong understanding of digital design principles, high-speed digital design, signal integrity, and clock domain crossing (CDC) - Experience with PCIe, Ethernet (10G/40G/100G), AXI, AXI-S, SPI, and I2C - Experience instantiating soft CPU cores such as RISC-V and using hard cores in SoC FPGAs - Experience integrating external memory including HBM and DDR Desired Skills: - Familiarity with C, C++, and Python for test scripting or embedded processor integration - Experience using version control systems such as Git or Perforce Compensation: Target base salary for this role is $160,000 – $220,000 per year, plus meaningful equity, benefits, and 401(k). Salary ranges are determined by role, experience, and location. #LI-EW1

ASIC Architect Who we are: We are a stealth-mode startup building foundational technology to address performance, scalability, and resiliency challenges in large-scale AI data center clusters. We are backed by top-tier VC firms and notable angel investors. The company is led by experienced builders and operators who have founded companies, taken them to scale, and exited successfully. We work with a strong sense of unity and shared responsibility, and we expect trust, integrity, and respect in how we collaborate and make decisions. We hold ourselves accountable to one another and to the quality of the work we deliver. Headquartered in Silicon Valley, we operate across a mix of remote and on-site locations in the U.S. and Canada. We aim to create an environment where people are treated fairly, supported in their growth, and are empowered to do meaningful work alongside others who take the craft seriously. What we need: We are seeking a highly skilled and visionary ASIC Architect to define, architect, and guide the development of next-generation, high-performance ASICs. As a key technical leader, you will translate high-level system requirements into detailed architectural specifications, balancing power, performance, and area (PPA) trade-offs. You will work across teams to define the architecture for IP blocks, sub-systems, and full SoC integration for advanced AI accelerators, networking, and datacenter computing workloads. Key Responsibilities: - Lead the creation of Architectural Design Specifications (ADS) and Micro-architecture Specifications (MAS) for complex ASICs. - Develop high-level performance models (using SystemC/TLM, C++, or Python) to analyze workload behaviors and validate architectural assumptions. - Optimize chip-level and block-level architecture to meet stringent power, performance, and area goals. - Define high-speed interconnect fabric, memory subsystems (DDR/HBM), and IO protocols (PCIe, CXL, UCIe). - Partner with RTL design, verification, physical design, firmware, and software teams to ensure seamless implementation and validation. - Drive architectural trade-off studies and lead design reviews. - Define advanced power management strategies including DVFS, power domains, and clock gating. - Mentor junior engineers and contribute to technical leadership across the organization. Required Skills and Qualifications: - Bachelor’s degree in Electrical Engineering, Computer Engineering, or Computer Science. - 7+ years of experience in ASIC architecture, micro-architecture, or high-level design. - Strong proficiency in SystemVerilog/Verilog and C/C++ or SystemC for modeling. - Deep knowledge of computer architecture, including CPU/GPU cores, caches, fabric, and memory hierarchies. - Experience with industry-standard protocols such as PCIe, DDR4/5, HBM, or CXL. - Familiarity with EDA tools such as Synopsys Design Compiler, Cadence Genus, or similar. - Experience with performance modeling and analysis tools. Desired Skills: - Master’s degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science. - Experience designing AI/ML accelerators or high-performance networking silicon. - Proven record of shipping high-performance silicon from concept to tape-out. - Familiarity with pre-silicon emulation platforms. - Strong scripting skills (Python, Tcl, Perl) for automation. - Excellent communication skills and ability to articulate complex architectural concepts. - Proactive problem solver capable of working with minimal oversight. - Strong leadership and mentorship capabilities. Compensation: Target base salary for this role is $160,000 - $220,000 per year + meaningful equity + benefits + 401k. Our salary ranges are determined by role, level, experience, and location.

Who we are: We are a stealth-mode startup building foundational technology to address performance, scalability, and resiliency challenges in large-scale AI data center clusters. We are backed by top-tier VC firms and notable angel investors. The company is led by experienced builders and operators who have founded companies, taken them to scale, and exited successfully. We work with a strong sense of unity and shared responsibility, and we expect trust, integrity, and respect in how we collaborate and make decisions. We hold ourselves accountable to one another and to the quality of the work we deliver. Headquartered in Silicon Valley, we operate across a mix of remote and on-site locations in the U.S. and Canada. We aim to create an environment where people are treated fairly, supported in their growth, and are empowered to do meaningful work alongside others who take the craft seriously. What we need This is a place to share your resume for any potential needs that are not featured on our page.

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This description is a summary of our understanding of the job description. Click on 'Apply' button to find out more. Role Description We are looking for a Software Development Engineer in Test (SDET) to ensure the reliability and performance of our core AI infrastructure. In this role, you are an engineer who builds sophisticated automation frameworks and stress-testing suites to break and then harden our system. You will be responsible for validating the intersection of distributed systems, GPU kernels, and AI frameworks. You will build a scalable foundation of trust in our code, ensuring that our performance-critical primitives work every time, at any scale. Key Responsibilities - Design, develop, and maintain a robust automated testing framework from the ground up that supports distributed AI training and inference workloads. - Develop complex test plans that go beyond unit tests, focusing on end-to-end system integration, stress testing, and hardware-software boundary conditions. - Partner closely with System Engineers to debug deep-seated issues in distributed clusters, using telemetry and profiling tools to identify bottlenecks. Qualifications - Strong proficiency in Python (for automation and orchestration). - Proven experience building or extending test automation frameworks for complex back-end systems. - Proven ability to troubleshoot automated test failures within complex large-scale distributed systems, and identify root causes. - Experience with containerization (Docker/Kubernetes) and modern CI/CD tools (GitHub Actions, GitLab CI, or Jenkins). Desired Skills - Experience with Kubernetes or Terraform or Ansible for managing test-bed environments. - Experience testing high-performance networking protocols or distributed file systems. - Experience testing software that interacts directly with drivers or firmware. Education - Bachelor's or Master's degree in Computer Engineering, Computer Science, or a related field. Compensation - Target base salary for this role is $140,000 - $200,000 per year + meaningful equity + benefits + 401k. - Our salary ranges are determined by role, level, experience, and location. Agency Note We do not accept resumes from agencies or search firms. Please do not forward candidate profiles through our careers page, email, LinkedIn messages, or directly to company employees. Any resumes submitted will be deemed the property of the company, and no fees will be paid in the event the candidate is hired.