This description is a summary of our understanding of the job description. Click on 'Apply' button to find out more. Role Description At Positron.ai, we are redefining the efficiency of AI Inference. As our Emulation Lead, you will be the architect of our pre-silicon validation strategy. You will take full ownership of our Cadence Palladium Z3 environment, bridging the gap between hardware design and system software. This is a high-impact role where you will build a specialized team to ensure our silicon is battle-tested and our software stack is production-ready long before the first chips return from the fab. Key Responsibilities - Ownership & Strategy: Define and execute the end-to-end emulation strategy for our next-generation AI Inference ASIC. - Infrastructure Management: - Oversee the complex, multi-site build process for emulation targets, ensuring design and software synchronization. - Manage builds and deployment of our Palladium Z3 cluster (hosted via Cadence Cloud). - Manage builds, job scheduling, and resource allocation. - Cross-Functional Synergy: Act as the primary technical bridge between the ASIC Design/DV teams and the System Software team. Ensure the emulation platform provides a high-fidelity environment for driver and compiler development. - Team Leadership: Recruit, mentor, and lead a lean, elite team of emulation specialists. - Environment Development: Oversee the creation of transactors, monitors, and complex testbenches. Drive the development of a comprehensive emulation testplan that targets both hardware bugs and software performance bottlenecks. - Debug & Analysis: Lead deep-dive debug sessions using Palladium’s advanced trace and capture capabilities to resolve complex SoC-level issues. Qualifications - 8+ years in ASIC/SoC verification or emulation, with at least 2+ years in a leadership or "Architect" capacity. - Deep, hands-on experience with Cadence Palladium systems (Z1, Z2, or Z3). Knowledge of the IXCOM/Dynamic Emulation interfaces is essential. - Proficiency in SystemVerilog/UVM for emulation-ready testbenches. - Strong understanding of high-speed interfaces (PCIe, CXL, DDR5) and AI-specific data flows. - Comfortable with scripting (Python, Tcl) to automate build flows and results analysis. - A proactive builder who prefers solving problems to filing tickets. You must be comfortable working in a fully remote, fast-paced environment. Requirements - Experience with AI/ML hardware accelerators or large-scale multi-core SoCs. - Familiarity with hybrid emulation (Virtual Platforms + Palladium). - Experience managing cloud-hosted hardware infrastructure. Benefits - Be part of a rapidly growing AI startup shaping the future of AI hardware. - Work on groundbreaking technology with a highly skilled and passionate team. - Competitive salary, equity, and comprehensive benefits package. - Flexible work environment with remote work options.

• Prototyping, integration, and development of drivers and components in embedded C for customer audio projects (TWS Earbuds, Headsets, Speakers) according to the product requirements based on the various SoCs, primarily focused on Qualcomm platforms, specifically the new S7 platform • Hardware/SW configurations and measurements during prototyping and pre-production • Developing unit and integration tests to verify software integrity using analysis tools to check for potential issues in our codebase

This description is a summary of our understanding of the job description. Click on 'Apply' button to find out more. Role Description - Develop test plans, writing testbenches and tests, and debugging any bugs found with the RTL team - Develop and execute verification plans for digital designs using SystemVerilog and UVM - Create and maintain testbenches, test cases, and test vectors - Contribute to the development of novel methodologies and verification techniques - Lead technical projects and mentorship of junior team members - Run simulations to verify design against specifications. Analyze results, identify issues, and debug designs - Implement coverage tracking and metrics - Document plans, environments, test cases, and all results for a comprehensive record of all verification strategies Qualifications - BSEE/MSEE with 15+ years of hands-on experience in SoC verification using UVM - Experience in Gate Level Simulation (GLS) setup and process corner failure analysis - Experience using Cadence verification tools such as Xcelium, SimVision, and JasperGold - Experience writing and debugging RTL using SystemVerilog - Programming experience using C, C++, and/or Python/Perl - Familiarity with digital design concepts and ASIC development flow Requirements - Experience verifying RISC-V based systems - Experience with emulation or FPGA prototyping - Experience with formal verification methodologies - Familiarity with the Chisel hardware description language - Experience verifying high-speed interfaces such as PCIe and DDR - Experience with version control systems (e.g., Git) and Continuous Integration/Continuous Deployment (CI/CD) pipelines Benefits - Competitive salary scaled based on experience - Bonus - Stock - Employer paid health care - Employer contribution to health savings account - Flexible time off - Flexible work location with remote options - 401K employer match

This description is a summary of our understanding of the job description. Click on 'Apply' button to find out more. Role Description - Assist with silicon bring-up - Contribute to all areas of SoC design, verification, and implementation - Design, implement and integrate complex SoC blocks - Develop block-level test cases to deliver fully functional designs - Develop micro-architecture specifications based on the SoC requirements - Develop synthesis constraints and resolve timing issues - Identify and resolve RTL and Gate-Level Simulation (GLS) failures at block and chip level - Participate in architectural feasibility studies - Participate in ECO implementation - Projects range from integrating third party IPs to designing complex systems - Resolve Lint, CDC, and DFT related issues Qualifications - BSEE/MSEE with 15+ years of SoC design/architecture experience - Clock domain crossing methodologies - Experience with RISC-V architecture - Logic synthesis and static timing analysis - Modeling SoC architectures with FPGAs - RTL Design including HVLs and HDLs (SystemVerilog, Verilog) - Scripting languages such as Python, Perl, Tcl, shell, etc. - SoC design flow including chip-level design, block/IP design and behavioral modeling - Strong familiarity with EDA tools - Strong problem solving and debugging capabilities - Third Party IP Integration experience - Working knowledge of PCIe and DDR - Working knowledge of standard bus protocols such as AXI/AMBA/TileLink - Working knowledge of SoC design with Chisel (plus) - Asynchronous logic design (plus) Benefits - Competitive salary scaled based on experience - Bonus - Stock - Employer paid health care - Employer contribution to health savings account - Flexible time off - Flexible work location with remote options - 401K employer match