Positron Corporation

Role Description As a Senior ASIC Design Engineer, you will take a leadership role in defining, implementing, and delivering critical IP blocks and subsystems for Positron.ai’s inference ASICs/SoCs. You will own the microarchitecture from high-level concept through RTL signoff, collaborating across architecture, verification, and physical design to achieve ambitious PPA and schedule goals. In addition to hands-on SystemVerilog design, you will mentor junior engineers, influence methodology, and drive key architectural tradeoffs that impact silicon performance and efficiency. Key Responsibilities - Microarchitecture & RTL Leadership: - Define and document microarchitecture for complex IP blocks/subsystems. - Deliver production-quality, parameterized SystemVerilog RTL with well-defined interfaces, power/clock intent, and embedded assertions. - Technical Ownership & Signoff: - Lead lint, CDC/RDC, DFT integration, and synthesis bring-up; collaborate with PD on floorplan and timing closure. - Own PPA metrics for assigned blocks and drive microarchitectural optimizations to meet targets. - Advanced Interface & Memory Integration: - Architect and integrate high-performance interconnects (AXI/CHI/ACE), DMA engines, coherency logic, and high-speed memory interfaces (HBM/DDR). - Engage with IP vendors and internal stakeholders to ensure seamless integration. - Methodology & Best Practices: - Develop and enforce coding guidelines, reusable IP packaging, and signoff checklists. - Contribute automation flows (Python/Tcl/Make/CI) to improve team efficiency. - Cross-Functional Collaboration: - Partner closely with Verification to define test plans and reference models. - Work with Architecture and Performance teams to correlate models against RTL. - Support bring-up, post-silicon debug, and customer engagements as required. - Mentorship & Technical Leadership: - Guide junior engineers in design techniques, methodology, and problem-solving. - Lead design reviews, drive consensus on tradeoffs, and advocate for best-in-class solutions. Qualifications - BS/MS in EE/CE (or related) with 8+ years of ASIC/SoC RTL design experience on complex, high-performance silicon. - Proven track record of leading designs from spec → microarchitecture → RTL → signoff with strong PPA outcomes. - Deep SystemVerilog RTL expertise, including clocking, resets, CDC/RDC handling, and protocol correctness. - Extensive experience with front-end flows/tools (lint, CDC, synthesis/STA, DFT) using major EDA suites. - Hands-on expertise with at least three of: HBM/DDR, PCIe/CXL, AMBA AXI/ACE/CHI, cache/memory hierarchies, high-throughput datapaths. - Strong cross-functional communication skills, capable of leading technical discussions and producing clear specifications. Preferred Qualifications - Background in AI/ML accelerator design (matrix/vector engines, compression, NoC bandwidth planning). - Formal verification/SVA expertise for property checking and design assertions. - Experience with low-power design techniques (clock-/power-gating, UPF/CPF). - Collaboration experience with cocotb/UVM for checkers and reference model co-development. - Familiarity with RISC-V subsystems, coherence protocols, or customer-owned tooling (COT) flows. Benefits - Shape the next generation of AI inference hardware with a high-caliber, collaborative team. - Take technical ownership of critical silicon components that directly impact product success. - Competitive salary + equity, comprehensive benefits, and flexible work environment. - Opportunities to innovate, lead, and grow your influence in a rapidly evolving space. Compensation and Benefits The base salary range for this role is $225,000 – $350,000. Please note that the figures provided represent the base salary range only and do not include other elements of our total compensation package, equity, or comprehensive benefits. At Positron AI, we value the unique expertise each candidate brings. While the range above reflects our typical expectation for the position, we reserve the flexibility to exceed this range for candidates whose specialized skills, significant experience, or unique qualifications fall outside the standard scope of the role. Final offers are determined based on a variety of factors, including internal equity, and individual impact.

Role Description As an ASIC Design Verification Engineer, you will play a critical role in ensuring the functional correctness and performance of our AI inference ASICs. You will be responsible for developing and executing advanced verification methodologies, working closely with design, architecture, and software teams to validate our silicon solutions. This is an opportunity to lead a talented team and contribute to the evolution of AI hardware technology. Key Responsibilities - Develop and execute verification strategies for AI inference ASICs - Define and implement comprehensive test plans and verification methodologies - Lead the development of verification environments using SystemVerilog UVM - Create and maintain simulation testbenches, directed and constrained-random tests - Collaborate with design and architecture teams to ensure functional coverage and closure - Drive debugging and root cause analysis of design issues in pre-silicon and post-silicon validation - Work with FPGA and emulation teams for early hardware validation - Manage verification schedules, deliverables, and risk mitigation plans Qualifications - Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field - 8+ years of experience in ASIC verification - Expertise in SystemVerilog UVM, and simulation tools - Strong knowledge of verification planning, testbench development, and coverage-driven verification - Experience with industry-standard EDA tools (Cadence, Synopsys, Mentor Graphics) - Hands-on experience with debugging tools, waveform analysis, and scripting (Python, Perl, or TCL) - Familiarity with AI/ML accelerators, memory subsystems, and high-speed interconnects - Proven track record of successfully verifying complex ASIC designs Requirements - Advanced degree in Electrical or Computer Engineering or related field - Experience with hardware-software co-verification - Knowledge of formal verification techniques - Understanding of post-silicon validation and bring-up methodologies Benefits - Be part of a rapidly growing AI startup shaping the future of AI hardware - Work on groundbreaking technology with a highly skilled and passionate team - Competitive salary, equity, and comprehensive benefits package - Flexible work environment with remote work options Compensation and Benefits The base salary range for this role is $200,000 – $350,000. Please note that the figures provided represent the base salary range only and do not include other elements of our total compensation package, equity, or comprehensive benefits. At Positron AI, we value the unique expertise each candidate brings. While the range above reflects our typical expectation for the position, we reserve the flexibility to exceed this range for candidates whose specialized skills, significant experience, or unique qualifications fall outside the standard scope of the role. Final offers are determined based on a variety of factors, including internal equity, and individual impact. Equal Opportunity Employer. If you’re excited about the role but don’t meet every bullet, we’d still love to hear from you.

Role Description We are looking for a Senior Technical Program Manager to own and drive three critical, concurrent workstreams at the intersection of hardware and software delivery: - Customer Deployments: Lead end-to-end programs for deploying Positron’s inference platform into customer environments, including hyperscalers and enterprise partners. Coordinate cross-functional execution across hardware, firmware, software, and partner integration teams to hit aggressive milestones from initial qualification through production ramp. - ASIC Emulation Software Deliverables: Drive the software deliverables required for ASIC emulation, including boot and runtime software that runs in the emulation environment itself, test infrastructure, validation environments, and tooling that enable pre-silicon software development and verification. Ensure the emulation software pipeline stays ahead of silicon timelines. - ASIC Software Releases (Pre- and Post-Silicon): Own the program management of ASIC software releases across the full silicon lifecycle—from early bring-up and emulation through tapeout, first silicon, and production software milestones. Define release timelines and scope for each release, and coordinate dependencies across compiler, runtime, driver, firmware, and platform software teams. This role sits within the Accelerator Platform Software (APS) organization and supports the broader Positron Software organization. It requires a TPM who thrives at the boundary of hardware and software, is comfortable with ambiguity, and can impose structure and accountability on complex, multi-team programs. A central responsibility across all three workstreams is managing the dependencies between hardware and software teams to ensure aligned delivery. Qualifications - 8+ years of technical program management experience in semiconductor, systems, or infrastructure software companies. - Direct experience managing programs that span ASIC/silicon development and software delivery—ideally across pre-silicon emulation through post-silicon production. - Track record of managing large-scale customer or partner deployment programs (hyperscaler experience strongly preferred). - Deep familiarity with silicon development milestones (RTL freeze, tapeout, A0/B0 silicon, qualification) and how software delivery maps to them. - Strong understanding of systems software stacks: compilers, runtimes, drivers, firmware, and platform/infrastructure software. - Demonstrated ability to build program structure in fast-moving, ambiguous environments—startup experience is a strong plus. - Excellent written and verbal communication; ability to present program status and risks clearly to executives, partners, and engineers alike. - BS or MS in Computer Science, Electrical Engineering, or a related technical field. Requirements - Own integrated program plans for customer deployments, including hyperscalers, coordinating deliverables across silicon, platform software, firmware, infrastructure, and partner-facing teams. - Define and manage release timelines, scope, and schedules for all ASIC software deliverables—pre-silicon (emulation, simulation, FPGA prototyping) and post-silicon (bring-up, validation, production releases). - Build and maintain a cross-functional dependency map that connects hardware milestones (tapeout, first silicon, qualification) to software readiness gates. - Manage dependencies between hardware and software teams across all workstreams, ensuring alignment on deliverables, handoffs, and integration schedules. - Drive weekly program reviews, track risks and blockers, and escalate with clarity and context to engineering leadership. - Partner with the customer’s technical program and engineering teams to manage joint milestones, deliverable handoffs, and integration checkpoints. - Establish and enforce release processes including branching strategy, qualification criteria, regression gates, and release notes for ASIC software drops. - Coordinate emulation platform resource allocation, boot and runtime software delivery, test scheduling, and environment readiness to maximize pre-silicon software velocity. - Create transparency across the organization through dashboards, status reports, and structured communication cadences. - Identify process gaps and implement lightweight, high-signal mechanisms that improve execution without adding bureaucracy. - Support hiring and onboarding as the Positron Software organization scales significantly. Benefits - The base salary range for this role is $150,000 – $300,000. - Please note that the figures provided represent the base salary range only and do not include other elements of our total compensation package, equity, or comprehensive benefits. - We reserve the flexibility to exceed this range for candidates whose specialized skills, significant experience, or unique qualifications fall outside the standard scope of the role. - Final offers are determined based on a variety of factors, including internal equity, and individual impact. Company Description Equal Opportunity Employer. If you’re excited about the role but don’t meet every bullet, we’d still love to hear from you.

This description is a summary of our understanding of the job description. Click on 'Apply' button to find out more. Role Description At Positron.ai, we are redefining the efficiency of AI Inference. As our Emulation Lead, you will be the architect of our pre-silicon validation strategy. You will take full ownership of our Cadence Palladium Z3 environment, bridging the gap between hardware design and system software. This is a high-impact role where you will build a specialized team to ensure our silicon is battle-tested and our software stack is production-ready long before the first chips return from the fab. Key Responsibilities - Ownership & Strategy: Define and execute the end-to-end emulation strategy for our next-generation AI Inference ASIC. - Infrastructure Management: - Oversee the complex, multi-site build process for emulation targets, ensuring design and software synchronization. - Manage builds and deployment of our Palladium Z3 cluster (hosted via Cadence Cloud). - Manage builds, job scheduling, and resource allocation. - Cross-Functional Synergy: Act as the primary technical bridge between the ASIC Design/DV teams and the System Software team. Ensure the emulation platform provides a high-fidelity environment for driver and compiler development. - Team Leadership: Recruit, mentor, and lead a lean, elite team of emulation specialists. - Environment Development: Oversee the creation of transactors, monitors, and complex testbenches. Drive the development of a comprehensive emulation testplan that targets both hardware bugs and software performance bottlenecks. - Debug & Analysis: Lead deep-dive debug sessions using Palladium’s advanced trace and capture capabilities to resolve complex SoC-level issues. Qualifications - 8+ years in ASIC/SoC verification or emulation, with at least 2+ years in a leadership or "Architect" capacity. - Deep, hands-on experience with Cadence Palladium systems (Z1, Z2, or Z3). Knowledge of the IXCOM/Dynamic Emulation interfaces is essential. - Proficiency in SystemVerilog/UVM for emulation-ready testbenches. - Strong understanding of high-speed interfaces (PCIe, CXL, DDR5) and AI-specific data flows. - Comfortable with scripting (Python, Tcl) to automate build flows and results analysis. - A proactive builder who prefers solving problems to filing tickets. You must be comfortable working in a fully remote, fast-paced environment. Requirements - Experience with AI/ML hardware accelerators or large-scale multi-core SoCs. - Familiarity with hybrid emulation (Virtual Platforms + Palladium). - Experience managing cloud-hosted hardware infrastructure. Benefits - Be part of a rapidly growing AI startup shaping the future of AI hardware. - Work on groundbreaking technology with a highly skilled and passionate team. - Competitive salary, equity, and comprehensive benefits package. - Flexible work environment with remote work options.