TYLsemi

Role Description As an SI/PI, Package and Power Delivery Engineer at Tylsemi, you will own signal integrity, power integrity, and package/PDN co-design across chip, package, and board interfaces. You will work closely with SoC, physical design, analog, package, board, and validation teams to ensure robust high-speed links, stable power delivery, and predictable signoff from early architecture through tapeout and bring-up. This role is ideal for engineers who enjoy cross-domain problem solving and turning complex electrical constraints into clean, manufacturable solutions. What You’ll Do - Drive SI/PI methodology and execution from early planning through signoff for high-speed interfaces and power delivery networks. - Perform package/board/chip co-design: define stackups, routing constraints, via strategies, reference planes, and return-path integrity. - Model and analyze high-speed channels (e.g., SerDes, DDR, PCIe, USB, Ethernet) including insertion/return loss, crosstalk, jitter, eye margins, and equalization tradeoffs. - Build and validate electrical models (IBIS/IBIS-AMI, S-parameters, SPICE) and ensure model correlation and version control hygiene. - Own PDN design and analysis across die/package/board: impedance targets, decap strategy, anti-resonance mitigation, and rail stability. - Run PI signoff including DC/AC IR drop, EM, dynamic droop/noise, and power/ground bounce; drive fixes with clear, reviewable action plans. - Partner with physical design and signoff teams on power grid architecture, bump/ball planning, current density limits, and rail partitioning. - Collaborate with package engineering on substrate routing, escape, ballout, and manufacturability constraints; review and approve package design deliverables. - Define and enforce design rules/constraints for routing, spacing, shielding, length matching, and reference plane transitions. - Support lab bring-up and correlation: translate silicon/package/board measurements into model updates and design improvements. - Create and maintain automation, checks, and reporting (Python/Tcl or equivalent) to improve predictability, repeatability, and execution speed. - Contribute to tapeout readiness: documentation, checklists, design reviews, and root-cause analysis to prevent recurrence. Qualifications - Hands-on experience delivering SI/PI and package/PDN solutions for complex SoCs (scope aligned to level of experience). - Strong fundamentals in transmission lines, S-parameters, impedance, return paths, coupling/crosstalk, and power delivery behavior across frequency. - Ability to translate system requirements into actionable constraints and to drive closure across multiple teams and design stages. - Methodical debug skills: clear problem statements, data-driven root cause, and practical mitigation plans. - Strong communication and engineering hygiene: reproducible analyses, clean documentation, and review-friendly deliverables. Requirements - Signal Integrity (SI) analysis for high-speed interfaces. - Power Integrity (PI) / PDN design and analysis (chip-package-board). - Package and power delivery co-design (substrate/ballout/bumps, stackup and routing constraints). - Electrical modeling (S-parameters, SPICE, IBIS/IBIS-AMI) and correlation mindset. - Cross-functional execution with SoC/PD/analog/package/board/validation teams. Nice to Have - Experience with industry tools for SI/PI and package analysis (e.g., HFSS, SIwave, ADS, HSPICE/Spectre, PowerSI, Clarity, Ansys RedHawk/Voltus or equivalents). - DDR/LPDDR and SerDes compliance experience (channel budgets, jitter/noise decomposition, margining). - Advanced packaging exposure (2.5D/3D, interposers, chiplets, HBM, CoWoS/EMIB-like concepts) and related SI/PI challenges. - Thermal-awareness in PDN/package decisions and collaboration with thermal/mechanical teams. - Experience defining signoff criteria, templates, and reusable flows across programs. Success in This Role Looks Like - Predictable SI/PI closure with clear milestones, risk tracking, and minimal late-stage surprises. - Robust package/PDN solutions that meet impedance/noise/jitter targets and scale cleanly to production. - Fast, high-quality debug and mitigation of SI/PI issues with strong cross-team alignment. - Well-documented, reproducible analyses and signoff artifacts that improve team velocity and tapeout readiness.

Role Description We are looking for a highly skilled RTL Designer to develop high-performance, scalable, and power-efficient digital designs for next-generation SoCs and Chiplets targeting AI, HPC, and Networking applications. This role requires deep expertise in RTL design, micro-architecture, and integration of high-speed interfaces, along with a strong focus on quality, performance, and first-time silicon success. Key Responsibilities - Design and implement high-quality RTL for complex SoC components and subsystems. - Own micro-architecture definition and execution for performance-critical blocks. - Develop designs that scale across IP, subsystem, and full SoC integration. - Integrate and optimize high-speed IO protocols such as: - PCIe / CXL - Ethernet (various speeds) - UCIe (chiplet interconnects) - Ensure robust design practices for: - Timing closure - Power efficiency - Area optimization - Collaborate closely with architecture, DV, physical design, and firmware teams. - Drive design quality initiatives including lint, CDC, RDC, and formal verification. - Support emulation, prototyping, and silicon bring-up. - Contribute to building reusable design components and IPs across multiple programs. - Leverage automation and AI tools to improve RTL productivity and design quality. Qualifications - Bachelor’s/Master’s degree in Electrical Engineering or related field. - 8+ years of experience in RTL design and micro-architecture. - Strong expertise in: - Verilog/SystemVerilog - Digital design fundamentals - High-performance and low-power design techniques - Experience designing for large SoCs in AI, HPC, or Networking domains. - Solid understanding of high-speed IO protocols: UCIe, PCIe, Ethernet. - Experience with multi-clock, high-bandwidth, and latency-sensitive designs. - Strong debugging and problem-solving skills. Preferred Qualifications - Experience with memory interfaces (DDR, HBM, LPDDR). - Familiarity with coherency protocols and interconnect fabrics. - Exposure to synthesis, STA, and physical design constraints. - Experience with emulation or FPGA prototyping. - Working knowledge of scripting (Python, Tcl). Key Attributes - Strong ownership and attention to detail. - Focus on quality and first-pass silicon success. - Ability to work across teams in a fast-paced environment. - Bias toward scalable, reusable, and clean design. Success Metrics - High-quality RTL with minimal re-spins. - Successful integration into complex SoCs. - Performance, power, and area targets met. - Contribution to reusable IP and design frameworks.

Role Description We are seeking a SoC Architect to define and drive the architecture of next-generation XPUs for AI Infrastructure. This role involves end-to-end ownership of system and SoC architecture, from concept to silicon, with a strong emphasis on scalability, performance, interconnects, and system-level optimization. - Define system architecture for complex SoCs, including compute, interconnect, memory, and IO subsystems. - Drive architecture for scalable and modular designs, including chiplet-based systems (UCIe). - Architect high-performance data movement across: - Compute engines (ARM/RISC-V/ML/MAC) - Memory subsystems (DDR/LPDDR/HBM) - IO interfaces (PCIe/UCIe/CXL/UALink/ESUN) - Collaborate with design and DV teams to ensure architectural feasibility and efficient implementation. - Develop performance models and simulations to validate architecture choices. - Drive trade-offs across: Performance, Power, Area and Cost. - Define system-level verification and validation strategies. - Work closely with customers and software teams to align architecture with real-world workloads. - Influence long-term roadmap and technology direction. Qualifications - Bachelor’s/Master’s/PhD in Electrical Engineering, Computer Engineering, or related field. - 18+ years of experience in SoC or system architecture. - Proven track record of architecting complex SoCs for AI, HPC, or Networking. - Deep understanding of: - System-level design and trade-offs. - High-speed IO protocols (UCIe, PCIe, Ethernet). - Data movement and interconnect design. - Experience with performance modeling and architectural simulation. - Strong cross-functional collaboration skills. Requirements - Experience with memory architectures (DDR, HBM, cache hierarchies). - Familiarity with chiplet architectures and advanced packaging (2.5D/3D). - Knowledge of coherency protocols (CXL, CHI). - Experience with power/performance optimization at system level. - Exposure to software-hardware co-design. Key Attributes - Strong system-level thinking and architectural vision. - Ability to balance innovation with practical execution. - High ownership and accountability. - Strong communication and leadership skills. Success Metrics - Scalable and efficient SoC architectures across multiple generations. - Achievement of performance, power, and cost targets. - Strong alignment between architecture and silicon outcomes. - Reduced architectural rework through early validation.

Role Description Own customer and ecosystem development for TylSemi's product portfolio. You will identify and qualify target accounts in the AI infrastructure market, engage architecture and procurement teams at hyperscalers and custom silicon builders, and translate customer platform requirements into product and roadmap inputs for R&D. You will also develop and manage relationships across the ecosystem — IP partners, OSATs, foundry ecosystem programs, and industry consortia. Responsibilities - Identify, qualify, and develop strategic accounts — hyperscalers, AI compute companies, and infrastructure semiconductor customers — from first contact through proposals and commercial agreement. - Engage customer architecture, platform, and procurement teams at the technical level; translate AI chip and chiplet platform requirements into actionable product specs for R&D. - Own the ecosystem partner map — IP vendors, OSATs, packaging partners, and foundry ecosystem programs; establish and maintain working relationships that support product and tape-out execution. - Drive participation in industry standards bodies and chiplet consortia (UCIe Consortium, PCI-SIG, CXL Consortium, OCP, IEEE, JEDEC etc.) to build visibility and influence roadmap alignment. - Develop and manage NDA pipeline, customer evaluation programs, and early-access engagements in coordination with engineering. - Produce and maintain account plans, pipeline tracking, and BD status reporting for leadership. - Represent TylSemi at industry events, customer briefings, and technical forums. Qualifications - 10+ years in business development, FAE, or customer/product management roles in semiconductors, with direct exposure to advanced AI chips, accelerators, or chiplet-based silicon. - Established relationships across hyperscaler silicon teams, AI chip startups, or custom ASIC customers; able to open doors at the architecture level, not just procurement. - FAE or CPM background strongly preferred — technical depth to engage R&D and platform teams credibly on chiplet integration, UCIe, PCIe, or power delivery topics. - Experience working the ecosystem side: IP vendors, foundry BD programs, OSAT, or packaging partners. - Track record of moving deals from first contact to signed agreement in a technical, long-cycle semiconductor sales environment. - Comfortable operating without a large support structure — this role owns its own pipeline, materials, and follow-through. - US-based; ability to travel for customer and industry engagements. Requirements - The pay range for this role is: 175,000 - 300,000 USD per year.

Role Description As Power Architecture Lead for PMIC, you will own the IVR architecture end-to-end — power conversion topology, digital control engine and analog subsystems. You will work directly with the Head of Engineering, digital architecture leads, and analog design team, and engage foundry partners and key customers at the architecture level. This role requires equal fluency in power electronics and mixed-signal IC design. You will define the architecture, validate the tradeoffs across topology, packaging, and thermal constraints, and drive execution through tape-out. Key Responsibilities - Architecture & Definition - Define IVR architecture: multi-phase interleaved buck converter topology, phase count configurability, switching frequency selection, and efficiency targets across load conditions. - Architect the digital control engine: per-phase duty cycle control, current balance, DVFS sequencing, and transient response optimization for AI workload dynamics. - Define the control and telemetry interface. - Establish power domain architecture for multi-domain compute targets: phase allocation, rail sequencing, and cross-domain coordination. - Define input power spec, inrush management, and integration requirements for in-package passive components including integrated inductors. - Mixed-Signal & Analog Oversight - Define requirements for analog subsystems: gate drivers, current sensing (DCR / integrated sense), on-chip thermal diodes, and oscillator / clock generation. - Oversee integrated inductor evaluation and selection — saturation current, DCR, Q-factor, and co-design with converter switching frequency. - Establish PVT corner strategy and margin targets across process, voltage, and temperature for all analog blocks. - Drive analog-digital co-design: ensure digital control loop stability across all PVT corners with defined phase margin and gain margin targets. - Define ESD and latch-up protection strategy for high-current power bumps. - Implementation Oversight - Guide process node selection for Gen 1 and roadmap generations — evaluate tradeoffs between power density, analog capability, and cost. - Lead IP evaluation for gate driver, ADC, and reference blocks; define custom vs. licensed IP strategy. - Drive DFT strategy for power chiplet: stuck-at fault coverage, analog BIST for converter calibration, and production test requirements. - Define packaging integration requirements. - Customer & Ecosystem Engagement - Translate AI compute platform power delivery requirements into product specifications — engage customers at the architecture level to validate rail counts, current targets, and transient profiles. - Interface with foundry partners on process capability, passive integration options, and packaging design rules. - Support technical due diligence for strategic partnerships and customer evaluations. - Roadmap & IP - Define the multi-generation architecture roadmap — establish a clear migration path from initial process node to advanced nodes with improved power density and packaging integration. Qualifications - 15+ years in power IC architecture; 5+ years at Principal level or higher in a fabless, IDM, or PMIC-focused semiconductor environment. - Deep expertise in multi-phase synchronous buck converter design — topology selection, loop compensation, stability analysis, and efficiency optimization across load. - Mixed-signal IC design fluency: gate driver design, current sensing techniques, analog control loops, and ADC/DAC integration in CMOS processes. - Hands-on experience with integrated passive components — on-chip or in-package inductors, capacitors, and their interaction with converter performance. - Advanced packaging familiarity: flip-chip, 2.5D/3D integration, bump map design, and thermal/electrical co-design for power-dense applications. - Experience driving power IC tape-outs from architecture definition through silicon bring-up and characterization. - Proficiency in power converter simulation: SPICE-level transient analysis, AC loop stability, and PVT corner sweeps. Preferred Qualifications - Experience with kilowatt-class power delivery for AI accelerators, GPUs, or high-performance CPUs is a big plus. - Familiarity with in-package voltage regulator architectures (FIVR, LEGO-style VR, or substrate-embedded passives). - Background in PMBus / I2C / proprietary digital power management interfaces — experience migrating from legacy interfaces to die-to-die control fabric is a plus. - Prior startup experience or comfort with early-stage technical ambiguity and fast-paced execution.

Role Description We are looking for a hands-on and highly strategic IT & Infrastructure Admin to build and manage the end-to-end compute, storage, network, and EDA infrastructure required for designing complex SoCs across digital and analog domains. This role goes beyond traditional IT—it requires deep ownership of EDA environments, compute strategy (cloud vs on-prem), cost optimization, and AI infrastructure enablement, ensuring high performance, scalability, and reliability for engineering teams. Key Responsibilities - EDA & Engineering Infrastructure - Own setup, deployment, and management of EDA tools and environments for digital design and verification, and analog and custom design flows. - Manage tool installations, upgrades, and compatibility across flows. - Drive EDA license management, including forecasting demand across teams and projects, optimizing utilization and cost, and vendor coordination and negotiations. - Ensure high availability and performance of compute farms and storage systems. - Compute & Platform Strategy - Define and execute strategy for cloud vs on-prem infrastructure. - Evaluate AWS (or other cloud platforms) vs owned/rented servers. - Build cost models and ROI analysis for different scaling scenarios. - Design scalable infrastructure for large regressions (DV workloads), RTL synthesis and physical design, and analog simulations (compute-intensive workloads). - Optimize job scheduling, workload distribution, and resource utilization. - Network & Systems Management - Design and manage high-performance network infrastructure for low-latency, high-throughput connectivity for EDA workloads. - Secure remote access for distributed teams. - Manage servers, storage (NAS/SAN), and backup systems. - Manage OS environments (primarily Linux-based). - Oversee data security, access control, and disaster recovery. - AI Infrastructure & Enablement - Support deployment and scaling of AI/ML infrastructure for engineering workflows. - Work with AI and engineering teams to enable AI agent workflows and optimize compute usage (GPU/CPU allocation). - Define and enforce AI usage guardrails, including data security and IP protection, and safe usage policies for internal and external AI tools. - Manage token usage, cost tracking, and access control for AI platforms. - Planning, Forecasting & Cost Optimization - Develop and maintain forecasts for compute infrastructure (cloud + on-prem), EDA licenses, and storage and network capacity. - Continuously optimize for cost vs performance vs scalability trade-offs. - Provide leadership with data-driven recommendations on infrastructure investments. Qualifications - Bachelor’s degree in Computer Science, Electrical Engineering, or related field. - 10+ years of experience in IT infrastructure / systems engineering, preferably in semiconductor or EDA environments. - Strong experience with EDA tool environments (Synopsys, Cadence, Siemens/Mentor). - Linux system administration. - Compute cluster management and job schedulers (LSF, Slurm, etc.). - Experience managing large-scale compute and storage systems. - Strong understanding of networking fundamentals (high-performance networks preferred). - Experience with cloud platforms (AWS preferred). Preferred Qualifications - Experience supporting SoC design teams (RTL, DV, Analog). - Familiarity with analog simulation environments and their compute demands. - Experience with hybrid cloud architectures. - Exposure to GPU infrastructure and AI/ML workloads. - Scripting skills (Python, Bash, etc.) for automation. - Experience with security and compliance in IP-sensitive environments. Key Attributes - Strong ownership and end-to-end accountability mindset. - Ability to balance technical depth with strategic decision-making. - Bias toward automation, scalability, and efficiency. - Strong problem-solving and operational excellence. - Comfortable working in a fast-paced startup environment. Success Metrics - Reliable, scalable infrastructure supporting high engineering productivity. - Optimized EDA license utilization and cost efficiency. - Effective cloud vs on-prem strategy with measurable ROI. - Minimal downtime and high system availability. - Secure and efficient AI infrastructure adoption. - Ability to scale infrastructure seamlessly with company growth.

Role Description As the HSIO Architect, you will own the high-speed interface architecture across the various product families. You will drive decisions from SerDes architecture to UCIe die-to-die integration, working directly with the Head of Engineering, digital leads, and analog teams. You will also serve as the technical interface to key IP vendors (UCIe PHY, SerDes), foundry partners, and anchor customers. This is not an IP integration role. We need someone who can define the architecture, validate the tradeoffs, and guide execution through tape-out. Key Responsibilities - Architecture & Definition - Define high-speed IO architecture for PCIe/Ethernet-224G/448G scale-up fabric/CPO-optics to electrical interfaces. - Define die-to-die interface architecture for UCIe integration: flit formats, credit-based flow control, sideband management, and latency targets. - Architect the SerDes-to-photonics interface, retimer integration, and co-packaged optics (CPO) readiness. - Own the signal integrity budget: TX/RX equalization, channel loss allocation, crosstalk margins, and jitter decomposition across the full channel. - Implementation Oversight - Guide SerDes PHY selection and evaluation; assess vendor IP (custom vs. licensed), and establish integration requirements. - Define and review UCIe PHY integration: bump map, power domain partitioning, analog/digital co-design requirements, and pad ring architecture. - Collaborate with digital architecture lead on protocol bridge design — PCIe TLP ↔ UCIe flit conversion, flow control, error handling. - Drive DFT and compliance test architecture for PCIe certification and UCIe conformance testing. - Establish PVT margin strategies and power management per-lane DVFS, shutdown sequences, and IVR chiplet coordination. - Customer & Ecosystem Engagement - Serve as primary technical interface to anchor customers and engaging hyperscaler architecture teams (AWS, Google, Microsoft, Meta) to validate product definition against platform requirements. - Roadmap & IP - Contribute to RTL reuse strategy — enabling derivative roadmap SKUs with minimal re-spin. - Identify and scope patentable innovations in UCIe integration, adaptive equalization, and multi-protocol bridge architectures. Qualifications - 15+ years in high-speed interface architecture; 5+ years at Principal level or higher in a fabless or IDM semiconductor environment. - Deep expertise in PCIe architecture — from PHY layer through controller and protocol stack; direct tape-out experience strongly preferred. - UCIe standard familiarity — flit-based transport, sideband protocol, and die-to-die integration in 2.5D/3D packages. - Signal integrity expertise: S-parameter analysis, channel simulation (HSPICE/IBIS-AMI), eye diagram closure, and crosstalk budgeting. - Experience with advanced nodes and advanced packaging (CoWoS, EMIB, InFO). - Track record of driving complex multi-party IP integrations from architecture through tape-out. Preferred Qualifications - Experience with 224G/400G+ SerDes architectures for scale-up AI fabric (NVLink, UALink, Ultra Ethernet, or proprietary). - Familiarity with electrical-optical co-design for CPO or near-package optics; EIC retimer or photonic interface experience. - Prior work in chiplet-based multi-die architectures — bumping strategy, KGD handling, heterogeneous integration. - PCIe-SIG membership or active contribution to UCIe Consortium working groups. - Prior startup experience or comfort with early-stage ambiguity and fast-paced execution.

Role Description As the HSIO Architect, you will own the high-speed interface architecture across the various product families. You will drive decisions from SerDes architecture to UCIe die-to-die integration, working directly with the Head of Engineering, digital leads, and analog teams. You will also serve as the technical interface to key IP vendors (UCIe PHY, SerDes), foundry partners, and anchor customers. This is not an IP integration role. We need someone who can define the architecture, validate the tradeoffs, and guide execution through tape-out. Key Responsibilities - Architecture & Definition - Define high-speed IO architecture for PCIe/Ethernet-224G/448G scale-up fabric/CPO-optics to electrical interfaces - Define die-to-die interface architecture for UCIe integration: flit formats, credit-based flow control, sideband management, and latency targets - Architect the SerDes-to-photonics interface, retimer integration, and co-packaged optics (CPO) readiness - Own the signal integrity budget: TX/RX equalization, channel loss allocation, crosstalk margins, and jitter decomposition across the full channel - Implementation Oversight - Guide SerDes PHY selection and evaluation; assess vendor IP (custom vs. licensed), and establish integration requirements - Define and review UCIe PHY integration: bump map, power domain partitioning, analog/digital co-design requirements, and pad ring architecture - Collaborate with digital architecture lead on protocol bridge design — PCIe TLP ↔ UCIe flit conversion, flow control, error handling - Drive DFT and compliance test architecture for PCIe certification and UCIe conformance testing - Establish PVT margin strategies and power management per-lane DVFS, shutdown sequences, and IVR chiplet coordination - Customer & Ecosystem Engagement - Serve as primary technical interface to anchor customers and engaging hyperscaler architecture teams (AWS, Google, Microsoft, Meta) to validate product definition against platform requirements - Roadmap & IP - Contribute to RTL reuse strategy — enabling derivative roadmap SKUs with minimal re-spin - Identify and scope patentable innovations in UCIe integration, adaptive equalization, and multi-protocol bridge architectures Qualifications - 15+ years in high-speed interface architecture; 5+ years at Principal level or higher in a fabless or IDM semiconductor environment - Deep expertise in PCIe architecture — from PHY layer through controller and protocol stack; direct tape-out experience strongly preferred - UCIe standard familiarity — flit-based transport, sideband protocol, and die-to-die integration in 2.5D/3D packages - Signal integrity expertise: S-parameter analysis, channel simulation (HSPICE/IBIS-AMI), eye diagram closure, and crosstalk budgeting - Experience with advanced nodes and advanced packaging (CoWoS, EMIB, InFO) - Track record of driving complex multi-party IP integrations from architecture through tape-out Preferred Qualifications - Experience with 224G/400G+ SerDes architectures for scale-up AI fabric (NVLink, UALink, Ultra Ethernet, or proprietary) - Familiarity with electrical-optical co-design for CPO or near-package optics; EIC retimer or photonic interface experience - Prior work in chiplet-based multi-die architectures — bumping strategy, KGD handling, heterogeneous integration - PCIe-SIG membership or active contribution to UCIe Consortium working groups - Prior startup experience or comfort with early-stage ambiguity and fast-paced execution

Role Description As an Analog Design Engineer at Tylsemi, you will design and deliver high-performance analog and mixed-signal circuits that enable robust, manufacturable silicon. This role spans a wide experience range (5–30 years) and is ideal for engineers who combine strong fundamentals with practical execution—translating system requirements into silicon-ready designs, validating performance across corners, and partnering closely with layout, verification, test, and product teams to drive first-time-right outcomes. - Own end-to-end analog block development: requirements definition, architecture, transistor-level design, simulation, and signoff - Design and optimize analog/mixed-signal circuits such as amplifiers, references, biasing, regulators (LDO/DC-DC support), comparators, oscillators/clocking, data converters (as applicable), and sensor/AFE front ends - Drive performance across PVT corners, mismatch/Monte Carlo, aging/reliability considerations, and realistic loading/interaction with surrounding blocks - Partner with layout to guide floorplanning, matching/guarding strategies, parasitic-aware design, and post-layout closure (PEX) - Develop and maintain testbenches, modeling collateral, and documentation to enable efficient verification and integration - Support silicon bring-up and debug: correlate lab data to simulations, root-cause issues, and implement design fixes or ECOs - Collaborate cross-functionally with digital, firmware, DFT, validation, and product engineering to ensure system-level success - Contribute to design methodology improvements: reusable circuits, checklists, signoff flows, and best practices that scale across programs Qualifications - 5+ years of experience in analog or mixed-signal IC design (scope and ownership aligned to experience level) - Strong fundamentals in analog circuit design, device physics, noise, stability/compensation, and feedback systems - Proficiency with industry-standard EDA tools and simulation flows (e.g., Spectre/HSPICE, ADE, waveform/debug tooling) - Experience closing designs through post-layout parasitics and across process/voltage/temperature corners - Ability to translate ambiguous system needs into clear block requirements and executable design plans - Strong debugging skills and comfort working with lab/validation teams to correlate silicon to simulation - Clear communication and high ownership in cross-site, cross-functional environments Requirements - Experience with high-speed or precision analog (low-noise, low-offset, high-linearity) depending on product needs - Background in power management (LDOs, bandgaps, references, protection, start-up, transient response) - ADC/DAC, PLL/clocking, or SERDES-adjacent analog experience - Familiarity with reliability/ESD considerations and design-for-manufacturability practices - Experience supporting production ramp: yield learning, characterization, and test correlation Success in This Role Looks Like - Analog blocks meet spec with margin across PVT, mismatch, and post-layout effects - Design reviews are crisp: requirements, tradeoffs, and risks are clearly articulated and managed - Silicon bring-up converges quickly through strong correlation, structured debug, and decisive fixes - Cross-functional partners (layout, verification, test, validation) can execute efficiently with clear interfaces and documentation - Reusable design collateral and improved methodology reduce cycle time and increase first-pass success

Role Description We are looking for a hands-on IT & Infrastructure Engineer to support and operate the compute, network, and EDA environments required for complex SoC design across digital and analog domains. This role will work closely with the IT & Infrastructure Architect to ensure reliable day-to-day operations while building scalable systems for EDA workflows, cloud infrastructure, and AI-enabled engineering environments. Key Responsibilities - EDA & Engineering Support - Install, configure, and maintain EDA tools and environments (Synopsys, Cadence, Siemens/Mentor) - Support engineers with: - Tool setup issues - Environment/debug problems - Flow execution challenges - Assist in EDA license management: - Monitoring usage - Basic forecasting inputs - Troubleshooting license issues - Compute & Systems Operations - Manage and maintain compute servers, clusters, and storage systems - Monitor system health, performance, and utilization - Support job schedulers (LSF, Slurm, etc.) and ensure smooth execution of workloads - Assist in managing cloud infrastructure (AWS or similar): - Instance setup and scaling - Basic cost tracking and optimization - Execute tasks related to cloud vs on-prem workloads under guidance - Network & IT Operations - Support network configuration and troubleshooting - Manage: - Linux systems and user environments - Access control and permissions - Backup and data management processes - Ensure uptime and responsiveness of infrastructure for engineering teams - AI Infrastructure Support - Assist in deployment and maintenance of AI/ML tools and platforms - Help manage: - API access and token usage - Resource allocation for AI workloads - Support implementation of AI usage policies and guardrails - Automation & Tooling - Write scripts (Python/Bash) to: - Automate routine tasks - Improve system efficiency - Simplify engineering workflows - Contribute to building repeatable and scalable infrastructure processes Qualifications - Bachelor’s degree in Computer Science, IT, Electronics, or related field - 3–7 years of experience in IT systems, infrastructure, or DevOps roles - Strong working knowledge of: - Linux system administration - Basic networking concepts - Scripting (Python, Bash, or similar) - Exposure to: - Compute clusters or server environments - Cloud platforms (AWS preferred) - Strong problem-solving and debugging skills Preferred Qualifications - Exposure to EDA environments (even at a basic level) - Familiarity with job schedulers (LSF, Slurm) - Experience supporting engineering teams or technical workloads - Basic understanding of AI/ML infrastructure or tools - Knowledge of storage systems (NFS, NAS, etc.) Key Attributes - Strong execution focus and willingness to get hands dirty - High responsiveness and support mindset toward engineering teams - Eagerness to learn EDA and semiconductor workflows - Attention to detail and reliability - Ability to work in a fast-paced startup environment Success Metrics - Fast resolution of infrastructure and tool issues - High system uptime and reliability - Smooth execution of EDA workflows and regressions - Improved efficiency through automation - Strong support satisfaction from engineering teams Growth Path This role is designed to grow into Senior Infrastructure Engineer, or Infrastructure/Platform Architect, with deeper ownership of EDA, cloud strategy, and AI platforms.