TYLsemi

Role Description Firmware & Embedded Software Architecture Leadership - Own the end-to-end firmware/embedded-software architecture for TYL chiplets. - On-die: - boot and secure boot - link sequencing - PCIe/CXL controller configuration and enumeration - address-translation (NTB/ATT) setup - MSI-X and AER handling - reset/FLR - power management - telemetry - in-field firmware update - Host-side: - kernel drivers - device-virtualization/transparency shim (synthetic PCIe device, VFIO-mdev-class) - management libraries/APIs - IOMMU (VT-d/SMMU) coordination - Define the hardware/software boundary with architecture and RTL — datapath (credit, ordering, merge/split, address-translation execution) in RTL; control plane in firmware — and own register maps and UCIe sideband/mailbox protocols. - Stay hands-on through first silicon. Bring-up, Methodology & Quality - Drive pre-silicon firmware and host-software development on emulation and virtual platforms, and lead post-silicon bring-up and debug. - Stand up the firmware engineering infrastructure: CI, automated and HIL testing, requirements traceability, secure-development practices (secure boot, attestation, key management), and the RAS/error-handling and fault-attribution strategy. - Define firmware release, quality, and security criteria across products and customers. Cross-functional & Customer Collaboration - Be the technical bridge between firmware/software and architecture, RTL, PHY/IP vendors and program management — bringing software feasibility into hardware decisions early. - Work directly with customers: compute-SoC partners on PCIe/CXL enablement, ATE/SLT integrators on the firmware and management libraries. Team Building & Management - Set technical direction, roadmap, and clear subsystem ownership (boot/security, PCIe/CXL management, host drivers and virtualization, RAS/telemetry). Qualifications - BS/MS in Electrical / Computer Engineering or Computer Science - 12+ years of embedded firmware development, with at least 5 years in silicon-level bring-up and validation of high-speed interface IPs. - Expert-level C and assembly for resource-constrained embedded CPUs (RISC-V or Arm Cortex-M/R class); strong debugging skills using JTAG/OpenOCD, trace, and logic analysers. - Deep PCIe expertise: link-training state machine, equalization (Gen3 EQ/LFSR, Gen4/5 preset search, Gen6/7 Flit Mode), speed-change sequences, LTSSM register-level behaviour. - Hands-on experience with HPC compute SoC firmware ecosystems — UEFI/BIOS bring-up, ACPI table authoring, SMBus/I2C/MCTP platform management, VT-d/IOMMU configuration — on HPC platforms. - Solid understanding of x86 server platform boot flow: SEC → PEI → DXE → BDS, PCIe enumeration in PEI/DXE, Option ROM interaction, and PCIe error-recovery paths (AER, DPC). - Experience with secure-boot architectures, code-signing flows, and OTA update mechanisms on embedded targets. - Comfortable working at the hardware-software boundary: reading RTL schematics, memory-mapped register specs, and waveforms from simulation or a logic analyser. Good To Have - CXL 2.0/3.0 firmware experience: HDM decoder programming, CXL IDE, DVSEC, BISnp coordination. - UCIe / die-to-die sideband firmware experience (RDI/FDI parameter negotiation, sideband messaging). - SPDM (DSP0274) and CMA device-attestation implementation experience. - Familiarity with PLDM for firmware update (DSP0267) and platform telemetry (DSP0248). - ATE scripting background — Teradyne UltraFLEX / Advantest T2000 board-level bring-up scripts. - Exposure to chiplet packaging concepts (UCIe, EMIB, CoWoS) and multi-die power-sequencing considerations. - Kernel-mode driver or UEFI DXE driver development experience.

Role Description We are looking for an experienced DFT Architect to lead Design-for-Test strategy, architecture definition, and implementation for complex ASIC/SOC designs across advanced technology nodes. The ideal candidate will drive end-to-end DFT architecture including scan, MBIST, compression, boundary scan, and at-speed test methodologies while collaborating with cross-functional teams to achieve high test coverage, quality, and silicon bring-up success. - Define and own SOC-level DFT architecture and test strategy for complex semiconductor designs. - Lead implementation of scan insertion, ATPG, MBIST, LBIST, boundary scan, and test compression methodologies. - Drive DFT planning and integration aligned with power, timing, area, and test coverage goals. - Collaborate with RTL, Physical Design, Verification, and Product Engineering teams for seamless DFT integration and signoff. - Analyze and resolve DFT-related timing, routing, and testability challenges. - Support silicon bring-up, debug, diagnosis, yield analysis, and production test optimization. - Develop and enhance DFT automation flows, methodologies, and reusable infrastructure. - Mentor junior engineers and provide technical leadership across projects. Qualifications - Bachelor’s or Master’s degree in Electronics, Electrical Engineering, VLSI, or related field. - 10+ years of experience in ASIC/SOC DFT implementation and architecture. - Strong expertise in scan, ATPG, MBIST, JTAG, compression, and low-power DFT methodologies. - Hands-on experience with industry-standard DFT tools such as Siemens Tessent, Synopsys DFT Compiler/TestMAX, or equivalent. - Strong understanding of RTL design, timing, physical design constraints, and silicon debug. - Experience with advanced technology nodes and large SOC integration. - Strong scripting and automation skills using Tcl, Python, Perl, or Shell. - Excellent leadership, problem-solving, and cross-functional collaboration skills. Requirements - Experience with automotive safety standards such as ISO 26262. - Exposure to chiplet-based architectures and 3D IC testing methodologies. - Knowledge of diagnosis-driven yield improvement and silicon analytics. Success in This Role Looks Like - Delivery of robust DFT architectures with high test coverage and efficient manufacturing test cost. - Successful silicon bring-up with minimal DFT-related issues. - Improved DFT methodology scalability, automation, and execution efficiency. - Strong technical leadership and contribution to organization-wide DFT best practices.

Role Description As an SI/PI, Package and Power Delivery Engineer at Tylsemi, you will own signal integrity, power integrity, and package/PDN co-design across chip, package, and board interfaces. You will work closely with SoC, physical design, analog, package, board, and validation teams to ensure robust high-speed links, stable power delivery, and predictable signoff from early architecture through tapeout and bring-up. This role is open across experience levels (5–20 years) and is ideal for engineers who enjoy cross-domain problem solving and turning complex electrical constraints into clean, manufacturable solutions. What You’ll Do - Drive SI/PI methodology and execution from early planning through signoff for high-speed interfaces and power delivery networks - Perform package/board/chip co-design: define stackups, routing constraints, via strategies, reference planes, and return-path integrity - Model and analyze high-speed channels (e.g., SerDes, DDR, PCIe, USB, Ethernet) including insertion/return loss, crosstalk, jitter, eye margins, and equalization tradeoffs - Build and validate electrical models (IBIS/IBIS-AMI, S-parameters, SPICE) and ensure model correlation and version control hygiene - Own PDN design and analysis across die/package/board: impedance targets, decap strategy, anti-resonance mitigation, and rail stability - Run PI signoff including DC/AC IR drop, EM, dynamic droop/noise, and power/ground bounce; drive fixes with clear, reviewable action plans - Partner with physical design and signoff teams on power grid architecture, bump/ball planning, current density limits, and rail partitioning - Collaborate with package engineering on substrate routing, escape, ballout, and manufacturability constraints; review and approve package design deliverables - Define and enforce design rules/constraints for routing, spacing, shielding, length matching, and reference plane transitions - Support lab bring-up and correlation: translate silicon/package/board measurements into model updates and design improvements - Create and maintain automation, checks, and reporting (Python/Tcl or equivalent) to improve predictability, repeatability, and execution speed - Contribute to tapeout readiness: documentation, checklists, design reviews, and root-cause analysis to prevent recurrence Qualifications - Hands-on experience delivering SI/PI and package/PDN solutions for complex SoCs (scope aligned to level of experience) - Strong fundamentals in transmission lines, S-parameters, impedance, return paths, coupling/crosstalk, and power delivery behavior across frequency - Ability to translate system requirements into actionable constraints and to drive closure across multiple teams and design stages - Methodical debug skills: clear problem statements, data-driven root cause, and practical mitigation plans - Strong communication and engineering hygiene: reproducible analyses, clean documentation, and review-friendly deliverables Requirements - Signal Integrity (SI) analysis for high-speed interfaces - Power Integrity (PI) / PDN design and analysis (chip-package-board) - Package and power delivery co-design (substrate/ballout/bumps, stackup and routing constraints) - Electrical modeling (S-parameters, SPICE, IBIS/IBIS-AMI) and correlation mindset - Cross-functional execution with SoC/PD/analog/package/board/validation teams Nice to Have - Experience with industry tools for SI/PI and package analysis (e.g., HFSS, SIwave, ADS, HSPICE/Spectre, PowerSI, Clarity, Ansys RedHawk/Voltus or equivalents) - DDR/LPDDR and SerDes compliance experience (channel budgets, jitter/noise decomposition, margining) - Advanced packaging exposure (2.5D/3D, interposers, chiplets, HBM, CoWoS/EMIB-like concepts) and related SI/PI challenges - Thermal-awareness in PDN/package decisions and collaboration with thermal/mechanical teams - Experience defining signoff criteria, templates, and reusable flows across programs Success in This Role Looks Like - Predictable SI/PI closure with clear milestones, risk tracking, and minimal late-stage surprises - Robust package/PDN solutions that meet impedance/noise/jitter targets and scale cleanly to production - Fast, high-quality debug and mitigation of SI/PI issues with strong cross-team alignment - Well-documented, reproducible analyses and signoff artifacts that improve team velocity and tapeout readiness Location - Bengaluru, India - Pune, India Experience - 5–20 years

Role Description TylSemi Solutions Private Limited is looking for a motivated and detail-oriented Design Verification Engineer to join our growing Verification team. In this role, you will contribute to the verification of cutting-edge SoCs and IPs targeting AI, HPC, and Networking applications. You will work closely with experienced verification engineers and architects to develop testbenches, create test scenarios, analyze coverage, and help ensure high-quality silicon delivery. This is an excellent opportunity for engineers who are passionate about digital design, verification methodologies, and next-generation semiconductor technologies. - Develop and execute verification test plans for IPs, subsystems, and SoC components. - Create and maintain SystemVerilog/UVM-based verification environments. - Write directed and constrained-random test cases to validate design functionality. - Develop functional coverage models and assist in coverage closure activities. - Debug simulation failures and collaborate with design engineers to resolve issues. - Write assertions (SVA) to improve design checking and verification quality. - Participate in regression execution, result analysis, and reporting. - Support IP integration and subsystem-level verification activities. - Learn and apply industry-standard verification methodologies and best practices. - Contribute to automation scripts for regression, reporting, and verification productivity. - Work closely with Design, Architecture, and Software teams to understand requirements and verify functionality. Qualifications - Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or related field. - 2–7 years of experience in Design Verification or Digital Design. - Strong understanding of digital design fundamentals and computer architecture. - Knowledge of: - Verilog/SystemVerilog - UVM methodology - Simulation and debugging concepts - Functional and code coverage - Basic scripting (Python, Perl, Shell, or TCL) - Familiarity with verification tools from Synopsys, Cadence, or Siemens EDA. - Understanding of common bus protocols such as AXI, APB, AHB, PCIe, or Ethernet is a plus. - Good analytical and debugging skills. - Strong communication and teamwork abilities. Preferred Qualifications - Internship or academic project experience in ASIC/SoC verification. - Exposure to SystemVerilog assertions (SVA). - Knowledge of constrained-random verification techniques. - Experience with Python-based automation. - Understanding of AI, HPC, or Networking architectures is a plus. - Familiarity with Git or other version-control systems. Key Attributes - Strong learning mindset and curiosity about semiconductor technologies. - Attention to detail and commitment to quality. - Problem-solving attitude with a willingness to learn from challenges. - Ability to work effectively in a collaborative environment. - Passion for innovation, automation, and continuous improvement.

Role Description As an SI/PI, Package and Power Delivery Engineer at Tylsemi, you will own signal integrity, power integrity, and package/PDN co-design across chip, package, and board interfaces. You will work closely with SoC, physical design, analog, package, board, and validation teams to ensure robust high-speed links, stable power delivery, and predictable signoff from early architecture through tapeout and bring-up. This role is ideal for engineers who enjoy cross-domain problem solving and turning complex electrical constraints into clean, manufacturable solutions. What You’ll Do - Drive SI/PI methodology and execution from early planning through signoff for high-speed interfaces and power delivery networks. - Perform package/board/chip co-design: define stackups, routing constraints, via strategies, reference planes, and return-path integrity. - Model and analyze high-speed channels (e.g., SerDes, DDR, PCIe, USB, Ethernet) including insertion/return loss, crosstalk, jitter, eye margins, and equalization tradeoffs. - Build and validate electrical models (IBIS/IBIS-AMI, S-parameters, SPICE) and ensure model correlation and version control hygiene. - Own PDN design and analysis across die/package/board: impedance targets, decap strategy, anti-resonance mitigation, and rail stability. - Run PI signoff including DC/AC IR drop, EM, dynamic droop/noise, and power/ground bounce; drive fixes with clear, reviewable action plans. - Partner with physical design and signoff teams on power grid architecture, bump/ball planning, current density limits, and rail partitioning. - Collaborate with package engineering on substrate routing, escape, ballout, and manufacturability constraints; review and approve package design deliverables. - Define and enforce design rules/constraints for routing, spacing, shielding, length matching, and reference plane transitions. - Support lab bring-up and correlation: translate silicon/package/board measurements into model updates and design improvements. - Create and maintain automation, checks, and reporting (Python/Tcl or equivalent) to improve predictability, repeatability, and execution speed. - Contribute to tapeout readiness: documentation, checklists, design reviews, and root-cause analysis to prevent recurrence. Qualifications - Hands-on experience delivering SI/PI and package/PDN solutions for complex SoCs (scope aligned to level of experience). - Strong fundamentals in transmission lines, S-parameters, impedance, return paths, coupling/crosstalk, and power delivery behavior across frequency. - Ability to translate system requirements into actionable constraints and to drive closure across multiple teams and design stages. - Methodical debug skills: clear problem statements, data-driven root cause, and practical mitigation plans. - Strong communication and engineering hygiene: reproducible analyses, clean documentation, and review-friendly deliverables. Requirements - Signal Integrity (SI) analysis for high-speed interfaces. - Power Integrity (PI) / PDN design and analysis (chip-package-board). - Package and power delivery co-design (substrate/ballout/bumps, stackup and routing constraints). - Electrical modeling (S-parameters, SPICE, IBIS/IBIS-AMI) and correlation mindset. - Cross-functional execution with SoC/PD/analog/package/board/validation teams. Nice to Have - Experience with industry tools for SI/PI and package analysis (e.g., HFSS, SIwave, ADS, HSPICE/Spectre, PowerSI, Clarity, Ansys RedHawk/Voltus or equivalents). - DDR/LPDDR and SerDes compliance experience (channel budgets, jitter/noise decomposition, margining). - Advanced packaging exposure (2.5D/3D, interposers, chiplets, HBM, CoWoS/EMIB-like concepts) and related SI/PI challenges. - Thermal-awareness in PDN/package decisions and collaboration with thermal/mechanical teams. - Experience defining signoff criteria, templates, and reusable flows across programs. Success in This Role Looks Like - Predictable SI/PI closure with clear milestones, risk tracking, and minimal late-stage surprises. - Robust package/PDN solutions that meet impedance/noise/jitter targets and scale cleanly to production. - Fast, high-quality debug and mitigation of SI/PI issues with strong cross-team alignment. - Well-documented, reproducible analyses and signoff artifacts that improve team velocity and tapeout readiness.

Role Description We are looking for a highly skilled RTL Designer to develop high-performance, scalable, and power-efficient digital designs for next-generation SoCs and Chiplets targeting AI, HPC, and Networking applications. This role requires deep expertise in RTL design, micro-architecture, and integration of high-speed interfaces, along with a strong focus on quality, performance, and first-time silicon success. Key Responsibilities - Design and implement high-quality RTL for complex SoC components and subsystems. - Own micro-architecture definition and execution for performance-critical blocks. - Develop designs that scale across IP, subsystem, and full SoC integration. - Integrate and optimize high-speed IO protocols such as: - PCIe / CXL - Ethernet (various speeds) - UCIe (chiplet interconnects) - Ensure robust design practices for: - Timing closure - Power efficiency - Area optimization - Collaborate closely with architecture, DV, physical design, and firmware teams. - Drive design quality initiatives including lint, CDC, RDC, and formal verification. - Support emulation, prototyping, and silicon bring-up. - Contribute to building reusable design components and IPs across multiple programs. - Leverage automation and AI tools to improve RTL productivity and design quality. Qualifications - Bachelor’s/Master’s degree in Electrical Engineering or related field. - 8+ years of experience in RTL design and micro-architecture. - Strong expertise in: - Verilog/SystemVerilog - Digital design fundamentals - High-performance and low-power design techniques - Experience designing for large SoCs in AI, HPC, or Networking domains. - Solid understanding of high-speed IO protocols: UCIe, PCIe, Ethernet. - Experience with multi-clock, high-bandwidth, and latency-sensitive designs. - Strong debugging and problem-solving skills. Preferred Qualifications - Experience with memory interfaces (DDR, HBM, LPDDR). - Familiarity with coherency protocols and interconnect fabrics. - Exposure to synthesis, STA, and physical design constraints. - Experience with emulation or FPGA prototyping. - Working knowledge of scripting (Python, Tcl). Key Attributes - Strong ownership and attention to detail. - Focus on quality and first-pass silicon success. - Ability to work across teams in a fast-paced environment. - Bias toward scalable, reusable, and clean design. Success Metrics - High-quality RTL with minimal re-spins. - Successful integration into complex SoCs. - Performance, power, and area targets met. - Contribution to reusable IP and design frameworks.

Role Description We are seeking a SoC Architect to define and drive the architecture of next-generation XPUs for AI Infrastructure. This role involves end-to-end ownership of system and SoC architecture, from concept to silicon, with a strong emphasis on scalability, performance, interconnects, and system-level optimization. - Define system architecture for complex SoCs, including compute, interconnect, memory, and IO subsystems. - Drive architecture for scalable and modular designs, including chiplet-based systems (UCIe). - Architect high-performance data movement across: - Compute engines (ARM/RISC-V/ML/MAC) - Memory subsystems (DDR/LPDDR/HBM) - IO interfaces (PCIe/UCIe/CXL/UALink/ESUN) - Collaborate with design and DV teams to ensure architectural feasibility and efficient implementation. - Develop performance models and simulations to validate architecture choices. - Drive trade-offs across: Performance, Power, Area and Cost. - Define system-level verification and validation strategies. - Work closely with customers and software teams to align architecture with real-world workloads. - Influence long-term roadmap and technology direction. Qualifications - Bachelor’s/Master’s/PhD in Electrical Engineering, Computer Engineering, or related field. - 18+ years of experience in SoC or system architecture. - Proven track record of architecting complex SoCs for AI, HPC, or Networking. - Deep understanding of: - System-level design and trade-offs. - High-speed IO protocols (UCIe, PCIe, Ethernet). - Data movement and interconnect design. - Experience with performance modeling and architectural simulation. - Strong cross-functional collaboration skills. Requirements - Experience with memory architectures (DDR, HBM, cache hierarchies). - Familiarity with chiplet architectures and advanced packaging (2.5D/3D). - Knowledge of coherency protocols (CXL, CHI). - Experience with power/performance optimization at system level. - Exposure to software-hardware co-design. Key Attributes - Strong system-level thinking and architectural vision. - Ability to balance innovation with practical execution. - High ownership and accountability. - Strong communication and leadership skills. Success Metrics - Scalable and efficient SoC architectures across multiple generations. - Achievement of performance, power, and cost targets. - Strong alignment between architecture and silicon outcomes. - Reduced architectural rework through early validation.

Role Description Own customer and ecosystem development for TylSemi's product portfolio. You will identify and qualify target accounts in the AI infrastructure market, engage architecture and procurement teams at hyperscalers and custom silicon builders, and translate customer platform requirements into product and roadmap inputs for R&D. You will also develop and manage relationships across the ecosystem — IP partners, OSATs, foundry ecosystem programs, and industry consortia. Responsibilities - Identify, qualify, and develop strategic accounts — hyperscalers, AI compute companies, and infrastructure semiconductor customers — from first contact through proposals and commercial agreement. - Engage customer architecture, platform, and procurement teams at the technical level; translate AI chip and chiplet platform requirements into actionable product specs for R&D. - Own the ecosystem partner map — IP vendors, OSATs, packaging partners, and foundry ecosystem programs; establish and maintain working relationships that support product and tape-out execution. - Drive participation in industry standards bodies and chiplet consortia (UCIe Consortium, PCI-SIG, CXL Consortium, OCP, IEEE, JEDEC etc.) to build visibility and influence roadmap alignment. - Develop and manage NDA pipeline, customer evaluation programs, and early-access engagements in coordination with engineering. - Produce and maintain account plans, pipeline tracking, and BD status reporting for leadership. - Represent TylSemi at industry events, customer briefings, and technical forums. Qualifications - 10+ years in business development, FAE, or customer/product management roles in semiconductors, with direct exposure to advanced AI chips, accelerators, or chiplet-based silicon. - Established relationships across hyperscaler silicon teams, AI chip startups, or custom ASIC customers; able to open doors at the architecture level, not just procurement. - FAE or CPM background strongly preferred — technical depth to engage R&D and platform teams credibly on chiplet integration, UCIe, PCIe, or power delivery topics. - Experience working the ecosystem side: IP vendors, foundry BD programs, OSAT, or packaging partners. - Track record of moving deals from first contact to signed agreement in a technical, long-cycle semiconductor sales environment. - Comfortable operating without a large support structure — this role owns its own pipeline, materials, and follow-through. - US-based; ability to travel for customer and industry engagements. Requirements - The pay range for this role is: 175,000 - 300,000 USD per year.

Role Description As Power Architecture Lead for PMIC, you will own the IVR architecture end-to-end — power conversion topology, digital control engine and analog subsystems. You will work directly with the Head of Engineering, digital architecture leads, and analog design team, and engage foundry partners and key customers at the architecture level. This role requires equal fluency in power electronics and mixed-signal IC design. You will define the architecture, validate the tradeoffs across topology, packaging, and thermal constraints, and drive execution through tape-out. Key Responsibilities - Architecture & Definition - Define IVR architecture: multi-phase interleaved buck converter topology, phase count configurability, switching frequency selection, and efficiency targets across load conditions. - Architect the digital control engine: per-phase duty cycle control, current balance, DVFS sequencing, and transient response optimization for AI workload dynamics. - Define the control and telemetry interface. - Establish power domain architecture for multi-domain compute targets: phase allocation, rail sequencing, and cross-domain coordination. - Define input power spec, inrush management, and integration requirements for in-package passive components including integrated inductors. - Mixed-Signal & Analog Oversight - Define requirements for analog subsystems: gate drivers, current sensing (DCR / integrated sense), on-chip thermal diodes, and oscillator / clock generation. - Oversee integrated inductor evaluation and selection — saturation current, DCR, Q-factor, and co-design with converter switching frequency. - Establish PVT corner strategy and margin targets across process, voltage, and temperature for all analog blocks. - Drive analog-digital co-design: ensure digital control loop stability across all PVT corners with defined phase margin and gain margin targets. - Define ESD and latch-up protection strategy for high-current power bumps. - Implementation Oversight - Guide process node selection for Gen 1 and roadmap generations — evaluate tradeoffs between power density, analog capability, and cost. - Lead IP evaluation for gate driver, ADC, and reference blocks; define custom vs. licensed IP strategy. - Drive DFT strategy for power chiplet: stuck-at fault coverage, analog BIST for converter calibration, and production test requirements. - Define packaging integration requirements. - Customer & Ecosystem Engagement - Translate AI compute platform power delivery requirements into product specifications — engage customers at the architecture level to validate rail counts, current targets, and transient profiles. - Interface with foundry partners on process capability, passive integration options, and packaging design rules. - Support technical due diligence for strategic partnerships and customer evaluations. - Roadmap & IP - Define the multi-generation architecture roadmap — establish a clear migration path from initial process node to advanced nodes with improved power density and packaging integration. Qualifications - 15+ years in power IC architecture; 5+ years at Principal level or higher in a fabless, IDM, or PMIC-focused semiconductor environment. - Deep expertise in multi-phase synchronous buck converter design — topology selection, loop compensation, stability analysis, and efficiency optimization across load. - Mixed-signal IC design fluency: gate driver design, current sensing techniques, analog control loops, and ADC/DAC integration in CMOS processes. - Hands-on experience with integrated passive components — on-chip or in-package inductors, capacitors, and their interaction with converter performance. - Advanced packaging familiarity: flip-chip, 2.5D/3D integration, bump map design, and thermal/electrical co-design for power-dense applications. - Experience driving power IC tape-outs from architecture definition through silicon bring-up and characterization. - Proficiency in power converter simulation: SPICE-level transient analysis, AC loop stability, and PVT corner sweeps. Preferred Qualifications - Experience with kilowatt-class power delivery for AI accelerators, GPUs, or high-performance CPUs is a big plus. - Familiarity with in-package voltage regulator architectures (FIVR, LEGO-style VR, or substrate-embedded passives). - Background in PMBus / I2C / proprietary digital power management interfaces — experience migrating from legacy interfaces to die-to-die control fabric is a plus. - Prior startup experience or comfort with early-stage technical ambiguity and fast-paced execution.

Role Description We are looking for a hands-on and highly strategic IT & Infrastructure Admin to build and manage the end-to-end compute, storage, network, and EDA infrastructure required for designing complex SoCs across digital and analog domains. This role goes beyond traditional IT—it requires deep ownership of EDA environments, compute strategy (cloud vs on-prem), cost optimization, and AI infrastructure enablement, ensuring high performance, scalability, and reliability for engineering teams. Key Responsibilities - EDA & Engineering Infrastructure - Own setup, deployment, and management of EDA tools and environments for digital design and verification, and analog and custom design flows. - Manage tool installations, upgrades, and compatibility across flows. - Drive EDA license management, including forecasting demand across teams and projects, optimizing utilization and cost, and vendor coordination and negotiations. - Ensure high availability and performance of compute farms and storage systems. - Compute & Platform Strategy - Define and execute strategy for cloud vs on-prem infrastructure. - Evaluate AWS (or other cloud platforms) vs owned/rented servers. - Build cost models and ROI analysis for different scaling scenarios. - Design scalable infrastructure for large regressions (DV workloads), RTL synthesis and physical design, and analog simulations (compute-intensive workloads). - Optimize job scheduling, workload distribution, and resource utilization. - Network & Systems Management - Design and manage high-performance network infrastructure for low-latency, high-throughput connectivity for EDA workloads. - Secure remote access for distributed teams. - Manage servers, storage (NAS/SAN), and backup systems. - Manage OS environments (primarily Linux-based). - Oversee data security, access control, and disaster recovery. - AI Infrastructure & Enablement - Support deployment and scaling of AI/ML infrastructure for engineering workflows. - Work with AI and engineering teams to enable AI agent workflows and optimize compute usage (GPU/CPU allocation). - Define and enforce AI usage guardrails, including data security and IP protection, and safe usage policies for internal and external AI tools. - Manage token usage, cost tracking, and access control for AI platforms. - Planning, Forecasting & Cost Optimization - Develop and maintain forecasts for compute infrastructure (cloud + on-prem), EDA licenses, and storage and network capacity. - Continuously optimize for cost vs performance vs scalability trade-offs. - Provide leadership with data-driven recommendations on infrastructure investments. Qualifications - Bachelor’s degree in Computer Science, Electrical Engineering, or related field. - 10+ years of experience in IT infrastructure / systems engineering, preferably in semiconductor or EDA environments. - Strong experience with EDA tool environments (Synopsys, Cadence, Siemens/Mentor). - Linux system administration. - Compute cluster management and job schedulers (LSF, Slurm, etc.). - Experience managing large-scale compute and storage systems. - Strong understanding of networking fundamentals (high-performance networks preferred). - Experience with cloud platforms (AWS preferred). Preferred Qualifications - Experience supporting SoC design teams (RTL, DV, Analog). - Familiarity with analog simulation environments and their compute demands. - Experience with hybrid cloud architectures. - Exposure to GPU infrastructure and AI/ML workloads. - Scripting skills (Python, Bash, etc.) for automation. - Experience with security and compliance in IP-sensitive environments. Key Attributes - Strong ownership and end-to-end accountability mindset. - Ability to balance technical depth with strategic decision-making. - Bias toward automation, scalability, and efficiency. - Strong problem-solving and operational excellence. - Comfortable working in a fast-paced startup environment. Success Metrics - Reliable, scalable infrastructure supporting high engineering productivity. - Optimized EDA license utilization and cost efficiency. - Effective cloud vs on-prem strategy with measurable ROI. - Minimal downtime and high system availability. - Secure and efficient AI infrastructure adoption. - Ability to scale infrastructure seamlessly with company growth.