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Senior ASIC Physical Design Engineer

TherapistTherapistFull TimeRemoteSeniorTeam 51-200

Location

United States

Posted

79 days ago

Salary

$170K - $250K / year

Seniority

Senior

No structured requirement data.

Job Description

Senior ASIC Physical Design Engineer

K2 Space

K2 is building the largest and highest-power satellites ever flown, unlocking performance levels previously out of reach across every orbit. Backed by $450M from leading investors including Altimeter Capital, Redpoint Ventures, T. Rowe Price, Lightspeed Venture Partners, Alpine Space Ventures, and others – with an additional $500M in signed contracts across commercial and US government customers – we’re mass-producing the highest-power satellite platforms ever built for missions from LEO to deep space. The rise of heavy-lift launch vehicles is shifting the industry from an era of mass constraint to one of mass abundance, and we believe this new era demands a fundamentally different class of spacecraft. Engineered to survive the harshest radiation environments and to fully capitalize on today’s and tomorrow’s massive rockets, K2 satellites deliver unmatched capability at constellation scale and across multiple orbits. With multiple launches planned through 2026 and 2027, we're Building Bigger to develop the solar system and become a Kardashev Type II (K2) civilization. If you are a motivated individual who thrives in a fast-paced environment and you're excited about contributing to the success of a groundbreaking Series C space startup, we’d love for you to apply. The Role We are seeking a Senior ASIC Physical Design Engineer to help implement advanced SoCs that power next-generation satellite and space systems. In this role, you will contribute to the full physical design flow—from synthesis to GDSII—working closely with architecture, RTL, verification, and packaging teams. You’ll be a key contributor in achieving timing closure, optimizing PPA, and supporting design integration with external partners. You will be part of a collaborative design team developing state-of-the-art mixed-signal SoCs to be hosted on some of the largest, most powerful, rapidly designed and rapidly manufactured satellites ever deployed in space. In your first 6 months, you will develop and implement new SoC sub-systems for satellite communications and beyond. In your first two years, you will have contributed to developing cutting-edge SoCs that will fly in space.  Responsibilities - Execute the complete physical design flow for complex SoC blocks and top-level integration, including synthesis, floorplanning, place & route, CTS, STA, and physical verification. - Perform timing closure and optimization across multiple corners and modes using industry-standard tools. - Collaborate with front-end, verification, and DFT teams to ensure clean handoff and predictable convergence. - Work with external physical design service providers and internal leads to review deliverables, resolve issues, and ensure schedule alignment. - Develop and maintain scripts and automation to improve flow efficiency and consistency. - Support physical sign-off activities including DRC/LVS, IR drop, EM, and power analysis. - Assist in chip-level integration, ECOs, and tapeout preparation. - Contribute to methodology development, tool evaluation, and flow documentation. - Support your product through production and spaceflight. Required Qualifications  - Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field. - 5–10 years of experience in ASIC physical design for complex SoCs. - Hands-on experience with industry-standard tools (Synopsys ICC2/Fusion Compiler, Cadence Innovus, or equivalent). - Strong understanding of timing analysis, power optimization, and physical verification flows. - Experience with hierarchical or flat SoC design methodologies. - Familiarity with FinFET technologies. - Working knowledge of DFT, UPF/CPF power intent, and ECO implementation. - Strong problem-solving skills and ability to work cross-functionally in fast-paced environments. Preferred Qualifications  - Exposure to radiation-hardened or space-qualified ASICs. - Experience with chip-package co-design or advanced packaging (2.5D/3D). - Familiarity with physical design service vendor management or offshore collaboration. - Experience with sign-off through TSMC. - Experience with Gate-All-Around technologies. - Experience working in cross-functional, geographically distributed teams. Compensation and Benefits: - Base salary range for this role is $170,000 – $250,000 + equity in the company - Salary will be based on several factors including, but not limited to: knowledge and skills, education, and experience level - Comprehensive benefits package including paid time off, medical/dental/vision/ coverage, life insurance, paid parental leave, and many other perks If you don’t meet 100% of the preferred skills and experience, we encourage you to still apply! Building a spacecraft unlike any other requires a team unlike any other and non-traditional career twists and turns are encouraged! If you need a reasonable accommodation as part of your application for employment or interviews with us, please let us know. Export Compliance As defined in the ITAR, “U.S. Persons” include U.S. citizens, lawful permanent residents (i.e., Green Card holders), and certain protected individuals (e.g., refugees/asylees, American Samoans). Please consult with a knowledgeable advisor if you are unsure whether you are a “U.S. Person.” The person hired for this role will have access to information and items controlled by U.S. export control regulations, including the export control regulations outlined in the International Traffic in Arms Regulation (ITAR). The person hired for this role must therefore either be a “U.S. person” as defined by 22 C.F.R. § 120.15 or otherwise eligible for a federally issued export control license. Equal Opportunity K2 Space is an Equal Opportunity Employer; employment with K2 Space is governed on the basis of merit, competence and qualifications and will not be influenced in any manner by race, color, religion, gender, national origin/ethnicity, veteran status, disability status, age, sexual orientation, gender identity, marital status, mental or physical disability or any other legally protected status.

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Full TimeRemoteTeam 51-200

K2 is building the largest and highest-power satellites ever flown, unlocking performance levels previously out of reach across every orbit. Backed by $450M from leading investors including Altimeter Capital, Redpoint Ventures, T. Rowe Price, Lightspeed Venture Partners, Alpine Space Ventures, and others – with an additional $500M in signed contracts across commercial and US government customers – we’re mass-producing the highest-power satellite platforms ever built for missions from LEO to deep space. The rise of heavy-lift launch vehicles is shifting the industry from an era of mass constraint to one of mass abundance, and we believe this new era demands a fundamentally different class of spacecraft. Engineered to survive the harshest radiation environments and to fully capitalize on today’s and tomorrow’s massive rockets, K2 satellites deliver unmatched capability at constellation scale and across multiple orbits. With multiple launches planned through 2026 and 2027, we're Building Bigger to develop the solar system and become a Kardashev Type II (K2) civilization. If you are a motivated individual who thrives in a fast-paced environment and you're excited about contributing to the success of a groundbreaking Series C space startup, we’d love for you to apply. The Role We are looking for a Principal ASIC Physical Design Engineer to lead the implementation of complex SoCs for next-generation satellite and space systems. You will own the full physical design flow—from RTL handoff to GDSII—and collaborate closely with architecture, RTL design, DFT, and packaging teams. This role also involves managing external physical design partners, driving tool and flow decisions, and ensuring first-pass silicon success in advanced FinFET technologies. You’ll be a key contributor in achieving timing closure, optimizing PPA, and supporting design integration with external partners. You will be part of a collaborative design team developing state-of-the-art mixed-signal SoCs to be hosted on some of the largest, most powerful, rapidly designed and rapidly manufactured satellites ever deployed in space. In your first 6 months, you will develop and implement new SoC sub-systems for satellite communications and beyond. In your first two years, you will have contributed to developing cutting-edge SoCs that will fly in space. Responsibilities - Own the complete RTL-to-GDSII flow: synthesis, floorplanning, place & route, clock tree synthesis (CTS), static timing analysis (STA), physical verification (DRC/LVS), and sign-off. - Develop and maintain physical design methodologies, scripts, and automation to optimize performance, power, and area (PPA). - Collaborate with front-end and verification teams to ensure clean handoffs, timing closure, and efficient design iteration. - Drive timing closure across multiple voltage and process corners, including sign-off with foundry-qualified tools. - Partner with package, SI/PI, and test teams for package-aware floorplanning and chip-to-board integration. - Manage and technically guide external physical design partners and service vendors, ensuring alignment on milestones, deliverables, and quality standards. - Work with EDA vendors to debug and optimize tool flows, and evaluate new methodologies. - Support chip bring-up and debug through close collaboration with post-silicon and test teams. - Support your product through production and spaceflight. Required Qualifications - Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field. - 10+ years of experience in ASIC physical design for high-performance SoCs. - Proven end-to-end expertise in RTL-to-GDSII flows using industry tools (Synopsys, Cadence, or Siemens). - Strong hands-on experience with timing closure, IR drop analysis, and ECO implementation. - Deep understanding of physical design constraints for multi-clock, multi-voltage, and hierarchical SoCs. - Experience with advanced FinFET process nodes. - Prior experience managing or coordinating offshore/outsourced PD teams or vendors. - Familiarity with DFT integration, STA sign-off, and power domain implementation (UPF/CPF). - Excellent communication, leadership, and cross-functional collaboration skills. - Act as technical leader and subject-matter expert helping to teach, grow, and mentor others in the team. Preferred Qualifications - Exposure to radiation-hardened or space-qualified ASICs. - Experience with chip-package co-design or advanced packaging (2.5D/3D). - Familiarity with physical design service vendor management or offshore collaboration. - Experience driving tapeouts through TSMC. - Experience with Gate-All-Around technologies. - Experience working in cross-functional, geographically distributed teams. Compensation and Benefits: - Base salary range for this role is $190,000 – $280,000 + equity in the company - Salary will be based on several factors including, but not limited to: knowledge and skills, education, and experience level - Comprehensive benefits package including paid time off, medical/dental/vision/ coverage, life insurance, paid parental leave, and many other perks If you don’t meet 100% of the preferred skills and experience, we encourage you to still apply! Building a spacecraft unlike any other requires a team unlike any other and non-traditional career twists and turns are encouraged! If you need a reasonable accommodation as part of your application for employment or interviews with us, please let us know. Export Compliance As defined in the ITAR, “U.S. Persons” include U.S. citizens, lawful permanent residents (i.e., Green Card holders), and certain protected individuals (e.g., refugees/asylees, American Samoans). Please consult with a knowledgeable advisor if you are unsure whether you are a “U.S. Person.” The person hired for this role will have access to information and items controlled by U.S. export control regulations, including the export control regulations outlined in the International Traffic in Arms Regulation (ITAR). The person hired for this role must therefore either be a “U.S. person” as defined by 22 C.F.R. § 120.15 or otherwise eligible for a federally issued export control license. Equal Opportunity K2 Space is an Equal Opportunity Employer; employment with K2 Space is governed on the basis of merit, competence and qualifications and will not be influenced in any manner by race, color, religion, gender, national origin/ethnicity, veteran status, disability status, age, sexual orientation, gender identity, marital status, mental or physical disability or any other legally protected status.

United States
$190K - $280K / year
Job Closed

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Speech-Language Pathologist (SLP) Spanish Speaking Remote

All Care Therapies

All Care Therapies, founded in 2009, is a healthcare provider specializing in physical, occupational, and speech therapy services. The organization delivers care through a hybrid m

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Company Description All Care Therapies provides speech, occupational, and physical therapy—virtually and in person. With clinics in California, Texas, and Nevada, we support clients of all ages and backgrounds. Our team is made up of passionate clinicians who value flexibility, collaboration, and meaningful care. Whether we’re helping a client communicate or supporting recovery after injury, we meet people where they are. Job Description We are hiring in all 50 states to provide services for clients in California. We are also offering reimbursement for California licensure! We are actively seeking part-time Speech Language Pathologists (SLPs) to join our Provider Network. You will have the opportunity to conduct treatment with our diverse client population of children and adults. We deliver skilled speech therapy services and interventions tailored to the unique needs of our clients with receptive and expressive language disorders, fluency, voice, and apraxia of speech. Responsibilities - Provide remote speech-language therapy services to clients - Conduct online speech-language assessments to determine eligibility for speech services - Develop, coordinate, implement, and monitor an individual's plan of care via teletherapy - Maintain a caseload of kids, adults, and the geriatric population - Keep appropriate and daily documentation Qualifications - ​​Master's degree in Speech-Language Pathology - Active CA State Speech Language Pathologist License or able to obtain a CA license - Experience in a clinic or school setting or successful clinical interview - Technical proficiency to conduct teletherapy through our all-inclusive platform - Should be comfortable working with children (18 months+) - Bilingual in Spanish required Location and Hours This is a 100% remote opportunity, requiring a minimum commitment of 12-29 hours per week for part-time. Compensation W2 | $43.00 - $56.00 per hour commensurate with experience, qualifications, and bilingualism. *Reimbursement for licensure(s) will be paid out after 145 hours of work. Why Join Us? Experience the difference of working with a close-knit team of dedicated therapists who value collaboration, mentorship, and shared professional growth. - Competitive compensation that recognizes your expertise - Flexible scheduling that empowers you to maintain work-life balance - A referral bonus program to reward your network - A clear pathway for career advancement through leadership development and internal promotion opportunities Join us and build a rewarding career in an environment that invests in your success. Additional Information All your information will be kept confidential according to EEO guidelines. All Care Therapies is an equal opportunity employer. All aspects of employment, including the decision to hire, promote, discipline, or discharge, will be based on merit, competence, performance, and business needs. We do not discriminate based on race, color, religion, marital status, age, national origin, ancestry, physical or mental disability, medical condition, pregnancy, genetic information, gender, sexual orientation, gender identity or expression, veteran status, or any other status protected under federal, state, or local law. - Department: Provider Network

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