ERM - Rina María Cabrera / Capgemini | North América External Resource Manager Tel.: +1 888 229 2961 Email: rina.cabrera@capgemini.com
Network Design Engineer
Location
United States
Posted
2 days ago
Salary
0
Seniority
Mid Level
Job Description
Network Design Engineer
Redolent, Inc
Role Description Job Description: Digital Design (RTL) Engineer Location: Santa Clara, CA Remote work option allowed. - Minimum 10 years of strong experience in Digital design at RTL level using Verilog/System Verilog. - Experience in developing micro architectural document from requirements specifications. - Experience developing designs from scratch. - Experience applying linting and other (QC) quality checking and basic verification of designs. - Experience supporting SoC designers in integration as needed. - Strong communication and collaboration skills. - Desirable but not essential experience: DMA, memory controller, MIPI DSI/CSI, data and control path pipeline design, interconnect and AMBA interfaces. - Candidate with design automation, scripting experience (Python) is preferable. - Develop HW architecture from specification documents. - Take complete responsibilities including writing RTL code for IP development/RTL integration, checking the code for Lint/CDC issues, checking synthesizability and timing quality of the design, checking low power implementation, supporting verification team with debug and supporting physical design teams on timing constraints and other design topics using Verilog/System Verilog/VHDL. - Develop and execute low power design (UPF/CPF). - Design top level RTL, integration of blocks, clocks, resets, configuration registers, etc. - Knowledge of JESD204C block design and related design/verification experience (includes licensed IP & PHY from 3rd parties). - Aware of DFT concepts to be used to fix functional violation that may get introduced including DFT structures. - Carry out static checks including Lint/CDC (Spyglass), synthesis, LEC and STA. Debugging and fixing functional breaks. - Take ownership of tasks and drive tasks to closure. - Synopsys/Cadence EDA Tools (Priority: 1). - LEC (Priority: 2). - STA/Constraints (Priority: 2). Qualifications - Minimum 10 years of strong experience in Digital design at RTL level using Verilog/System Verilog. - Strong communication and collaboration skills. Requirements - Experience in developing micro architectural document from requirements specifications. - Experience developing designs from scratch. - Experience applying linting and other (QC) quality checking and basic verification of designs. - Experience supporting SoC designers in integration as needed. Benefits - Remote work option allowed.
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UnisysUnisys is proud to be an equal opportunity employer that considers all qualified applicants without regard to age, caste, citizenship, color, disability, family medical history, family status, ethnicity, gender, gender expression, gender identity, genetic information, marital status, national origin, parental status, pregnancy, race, religion, sex, sexual orientation, transgender status, veteran status or any other category protected by law. This commitment includes our efforts to provide for all those who seek to express interest in employment the opportunity to participate without barriers. If you are a US job seeker unable to review the job opportunities herein, or cannot otherwise complete your expression of interest, without additional assistance and would like to discuss a request for reasonable accommodation, please contact our Global Recruiting organization at GlobalRecruiting@unisys.com or alternatively Toll Free: 888-560-1782 (Prompt 4). US job seekers can find more information about Unisys’ EEO commitment here.
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