Distro is a marketplace to find, hire, and pay technical talent in over 200 countries. Join now for free.
Senior/Lead ASIC Engineer
Location
Peru
Posted
19 days ago
Salary
$80 - $90 / hour
Seniority
Senior
Job Description
Senior/Lead ASIC Engineer
Distro
• Lead DFT architecture, implementation & sign-off • Drive scan insertion, scan chains & compression flows • Own MBIST/LBIST integration and debug • Perform silicon debug, failure analysis & root cause • Develop DFT constraints (SDC) & timing analysis • Support ATPG generation, simulation & coverage closure • Work on JTAG, boundary scan, iJTAG • Collaborate across RTL, PD, STA, validation teams • Mentor junior engineers • Develop automation scripts (TCL/Perl/Python)
Job Requirements
- 10+ years in ASIC DFT (hands-on)
- Strong DFT fundamentals & fault models knowledge
- Expertise in scan, ATPG, MBIST, JTAG, debug
- Experience with Synopsys / Cadence / Siemens tools
- Post-silicon validation experience
- Large SoC & hierarchical DFT exposure
Related Guides
Related Categories
Related Job Pages
More Hardware Engineer Jobs
Senior EDA Tools and Systems Support Hardware Engineer
CiscoWe securely connect everything to make anything possible.
• Provide expert-level support for ECAD tools, specifically focusing on schematic capture and PCB layout workflows, with a broad understanding of EDA tools in general. • Develop and maintain scripts (using Python, Perl, or similar languages) to automate design tasks, improve data integrity, and streamline the design-to-manufacturing flow. • Manage and maintain Linux-based EDA environments; provide secondary support for Windows-based design workstations. • Manage EDA license servers, monitor usage, and troubleshoot checkout issues to ensure maximum availability for the design team. • Coordinate tool upgrades, patch rollouts, validation, and associated user communication and training. • Create and maintain technical documentation, standard operating procedures (SOPs), internal best practices, support knowledge bases, and user guides for the design community.
ASIC Packaging Signal/Power Integrity Hardware Engineering Technical Lead
CiscoWe securely connect everything to make anything possible.
• Develop, document, and implement design rules for ultra-high-speed signaling • Analyze substrate signal integrity (SI) and power integrity (PI) • Design, document, and develop ASIC packages for high-volume, high-quality release • Collaborate with system partners, vendors, and design leads • Define the processes, methods, and tools for the design and implementation of complex ASIC/package developments • Lead or participate in chip architecture discussions and the definition, architecture, and design of high-performance ASICs • Mentor and support the signal integrity team and junior engineers • Develop and promote a culture of design reviews, postmortems, and continuous improvement across multi-disciplined engineering teams
Anti-Tamper Systems/Hardware Engineer
Archarithms IncArcarithm is located in beautiful, downtown Huntsville, AL, one of the fastest growing cities in the U.S.! We cultivate and foster an environment of integrity, open communication, work-life balance, and career development. We are excited to continue to change and improve the world through innovation and technology!
Role Description The Anti-Tamper Systems/Hardware Engineer will support the Missile Defense Agency (MDA) Command and Control, Battle Management, and Communications (C2BMC) program by developing, implementing, and maintaining Anti-Tamper (AT), Program Protection (PP), Critical Program Information (CPI), and Defense Exportability strategies. The position supports risk assessments, system protection planning, verification and validation efforts, milestone reviews, and customer engagement activities to ensure protection of critical technologies and program assets. Key Responsibilities - Coordinate with Missile Defense Agency (MDA) Anti-Tamper (AT) and C2BMC leadership regarding updates and changes to the C2BMC system. - Perform Anti-Tamper Risk and Threat Management Assessments and prepare associated reports. - Develop analysis processes and prepare Anti-Tamper plans while providing coordination and input for near-term fielding decisions. - Develop, deliver, and maintain: - C2BMC Anti-Tamper Plan - C2BMC Anti-Tamper Evaluation Plan - C2BMC Key Management Plan - C2BMC Program Protection Plan - Develop, deliver, and maintain: - Critical Program Information (CPI) analyses - Defense Exportability Assessments - Defense Export Strategy documentation - Develop, deliver, and maintain waivers for CPI, Anti-Tamper, and Defense Exportability features. - Identify risk-based technical countermeasures to protect C2BMC Critical Program Information and Critical Components. - Develop recommendations that improve program protection while balancing cost, schedule, and performance objectives. - Assess program Anti-Tamper and Program Protection designs and implementation plans in support of verification and validation efforts. - Support program milestone reviews and fielding decisions. - Verify that Anti-Tamper and Program Protection products meet entrance criteria and receive required approvals. - Brief Anti-Tamper and Program Protection requirements to stakeholders. - Prepare white papers, technical evaluations, and supporting documentation. - Interact with customers to define System Security Engineering (SSE) requirements, solutions, trade studies, implementation approaches, system impacts, costs, and effectiveness. - Support development of plans, cost estimates, task execution strategies, project tracking, reporting, and risk mitigation activities. - Keep senior management informed of major accomplishments, issues, risks, and concerns. Qualifications - Advanced degree with 7+ years of relevant experience; Bachelor's degree with 9+ years of relevant experience; or equivalent combination of education and experience. - Demonstrated ability to apply extensive technical expertise. - Ability to solve complex problems requiring ingenuity, creativity, and independent judgment. - Work is performed with minimal supervision and reviewed primarily for achievement of objectives. - Erroneous decisions could significantly impact organizational objectives. - May serve in project leadership roles and act as primary customer contact on significant technical matters. Preferred Skills - Demonstrated ability to collaborate across multi-site and multi-disciplinary teams. - Ability to translate high-level requirements into an evolving Minimum Viable Product (MVP) leading to fielded solutions. - Excellent written and verbal communication skills. - Ability to clearly communicate technical approaches, recommendations, and findings. - Experience developing and implementing engineering plans. - Proven success working in collaborative team environments. - Demonstrated experience performing duties similar to those described in this position. - Experience designing automation pipelines that support agile development in rapidly changing environments. - Understanding of Anti-Tamper and Defense Exportability requirements and secure hardware/software methodologies. - Ability to work independently in highly dynamic environments. - Self-starter capable of conducting research and documenting results effectively. Travel Requirements - Some travel between Colorado Springs (COS) and Huntsville (HSV) development sites may be required.
• Identify and drive Critical Item and Technology (CIT) action plans to closure throughout hardware development to increase product and process maturity during the development phase on a program • Lead implementation of NPI requirements, including Design‑to‑Cost, Design for Excellence/Producibility, prototyping, and supplier technical risk mitigation on a program • Develop and document the Producibility and Prototyping strategy within the Hardware Development Plan on a program • Ensure timely and effective execution of Producibility, Prototyping, and Supplier Technical Support activities starting in development and into early production on a program • Support or facilitate Design for Manufacturing and Assembly (DFMA) workshops to identify Cost Reduction Opportunities (CROs) and drive execution of Cost Reduction Initiatives (CRIs) on a program • Baseline and monitor risks and opportunities related to predictive manufacturing yield, cost, and throughput for Critical Items and Technologies using Valor DFM, PCAT Pro, DFMPro, Siemens VSA, CETOL, and other hardware optimization tools on a program • Drive identification of Critical and Key Characteristics and implement/manage production Control Plans to manage technical risks to production on a program • Ensure robust supplier capability assessments, supplier selection, technical requirements understanding, and production readiness on a program to meet cost, quality, and schedule needs • Deliver proactive supplier support by conducting onsite visits, driving clear communication between stakeholders and suppliers, resolving supplier requests and manufacturing defects, and reviewing supplier data and lessons learned to advance continuous improvement in manufacturing, assembly, test, and inspection • Serve as a liaison between CPR Section Leaders, Program CEs, IPTLs, Producibility Engineers, and cross‑functional teams to maintain consistent communication, alignment, and program execution • Collaborate with the CE, IPTLs, and REAs to prepare for NPI assessments and manage associated actions on a program • Compile producibility artifacts, generate memos, and present producibility analysis to the customer when contractually required


