Role Description - Develop test plans, writing testbenches and tests, and debugging any bugs found with the RTL team - Develop and execute verification plans for digital designs using SystemVerilog and UVM - Create and maintain testbenches, test cases, and test vectors - Contribute to the development of novel methodologies and verification techniques - Lead technical projects and mentorship of junior team members - Run simulations to verify design against specifications. Analyze results, identify issues, and debug designs - Implement coverage tracking and metrics - Document plans, environments, test cases, and all results for a comprehensive record of all verification strategies Qualifications - BSEE/MSEE with 15+ years of hands-on experience in SoC verification using UVM - Experience in Gate Level Simulation (GLS) setup and process corner failure analysis - Experience using Cadence verification tools such as Xcelium, SimVision, and JasperGold - Experience writing and debugging RTL using SystemVerilog - Programming experience using C, C++, and/or Python/Perl - Familiarity with digital design concepts and ASIC development flow Requirements - Experience verifying RISC-V based systems - Experience with emulation or FPGA prototyping - Experience with formal verification methodologies - Familiarity with the Chisel hardware description language - Experience verifying high-speed interfaces such as PCIe and DDR - Experience with version control systems (e.g., Git) and Continuous Integration/Continuous Deployment (CI/CD) pipelines Benefits - Competitive salary scaled based on experience - Bonus - Stock - Employer paid health care - Employer contribution to health savings account - Flexible time off - Flexible work location with remote options - 401K employer match

Role Description Own and be responsible for pre-tape out quality for digital SOC modules on the MCU. - Explore architecture and develop micro-architecture. - RTL development for IPs and SOCs using Verilog. - 3rd party IP identification, selection, and integration. - Collaboration with verification and FPGA teams in test plan development and debug. - Collaborate with the Physical Design team to close the design on timing and power targets. - Assist in silicon bring-up and validation. - Run tool for quality checks (LINT, CDC, and RDC) and fix/waive the issues. Qualifications - Bachelor’s degree in Electronics Engineering, Electrical Engineering, Instrumentation & Control Engineering, or a related field, plus 20 years of experience. - Possess deep and broad knowledge of current and emerging SOC design technologies. - Have expert knowledge in designing, implementing, and troubleshooting IPs and SOC. - Demonstrate a deep understanding of customer needs and the competitive landscape. - Ability to estimate the impact of and help plan and lead the implementations and have a positive impact on the entire output. - Can architect and guide programs across the full range of technical areas. Requirements - We're seeking passionate technologists who thrive on pushing the boundaries, solving complex challenges, and driving transformative solutions. - At Ambiq, you'll collaborate with a dynamic team that values relentless innovation, customer-centric thinking, and continuous learning. - If you're a self-motivated, creative problem-solver eager to push technological limits and make a meaningful impact in energy efficiency, this is your opportunity to grow, excel, and turn groundbreaking ideas into reality. Benefits - Innovate: We tenaciously find ways to break down the barriers to possible solutions. - Collaborate: We proactively communicate and encourage each other to be better. - Focus: We keep the voice of the customer at the center of everything we do. - Learn: We strive for continuous improvement and are always curious. - Achieve: We execute on quality and follow through on our commitments.

The application window is expected to close on 12/31/25 Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received. This role can be performed from any location within the United States. Meet the Team Join our team at Acacia, where we design advanced optical transceivers for high-speed fiber optic transmission in data centers and telecommunication networks. We're seeking enthusiastic, experienced individuals to work on the forefront of fiber optic technology. You'll be part of the team developing Digital Signal Processing (DSP) and Forward Error Correction (FEC) algorithms for our optical transceivers' Application-Specific Integrated Circuits (ASICs). Collaboration with colleagues from the DSP and ASIC teams is key to optimizing performance and power efficiency. You'll contribute to system design, develop architectures, and support ASIC design and verification. Work closely with colleagues across various fields and gain diverse knowledge in optical system testing, analog components, modeling, and more. Your Impact With your expertise in DSP for coherent optical transceivers, FEC, and modeling, you help the team to develop the next generation of low-power and high-performance coherent transceivers. Here are some examples of possible topics: * Invent, simulate and validate new DSP or FEC algorithms (both in floating-point and fixed-point precision) to improve performance and functionality or lower power consumption * Test and optimize these algorithms on actual hardware and correlate performance with previous simulations * Develop models of analog RF and optical components and evaluate system performance with these models * Analyze performance of developed transceiver modules and update models and simulation environments to accurately match the measured results Minimum Qualifications: Typically: Bachelors + 15 years of related experience, or Masters + 12 years of related experience, or PhD + 8 years of related experience * + 10 years of industry experience in related fields. * Experience with Digital Signal Processing (DSP) and/or Forward Error Correction (FEC) for coherent optical communications. * Experience in modeling communication systems. * Programming experience in C/C++, Python, Matlab, or similar languages. * A master's or Ph.D. degree in mathematics, physics, or electrical engineering is highly recommended, although not strictly required. Preferred Qualifications: A master's or Ph.D. degree in mathematics, physics, or electrical engineering is highly recommended, although not strictly required. * Experience with C++, Linux, and version control systems, specifically SVN and Perforce. * Experience with Verilog or VHDL, and/or collaboration with ASIC designers. * Experience presenting technical information to colleagues. Why Cisco? At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint. Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere. We are Cisco, and our power starts with you. Message to applicants applying to work in the U.S. and/or Canada: The starting salary range posted for this position is $225,000.00 to $325,300.00 and reflects the projected salary range for new hires in this position in U.S. and/or Canada locations, not including incentive compensation*, equity, or benefits. Individual pay is determined by the candidate's hiring location, market conditions, job-related skillset, experience, qualifications, education, certifications, and/or training. The full salary range for certain locations is listed below. For locations not listed below, the recruiter can share more details about compensation for the role in your location during the hiring process. U.S. employees are offered benefits, subject to Cisco’s plan eligibility rules, which include medical, dental and vision insurance, a 401(k) plan with a Cisco matching contribution, paid parental leave, short and long-term disability coverage, and basic life insurance. Please see the Cisco careers site to discover more benefits and perks. Employees may be eligible to receive grants of Cisco restricted stock units, which vest following continued employment with Cisco for defined periods of time. U.S. employees are eligible for paid time away as described below, subject to Cisco’s policies: - 10 paid holidays per full calendar year, plus 1 floating holiday for non-exempt employees - 1 paid day off for employee’s birthday, paid year-end holiday shutdown, and 4 paid days off for personal wellness determined by Cisco - Non-exempt employees** receive 16 days of paid vacation time per full calendar year, accrued at rate of 4.92 hours per pay period for full-time employees - Exempt employees participate in Cisco’s flexible vacation time off program, which has no defined limit on how much vacation time eligible employees may use (subject to availability and some business limitations) - 80 hours of sick time off provided on hire date and each January 1st thereafter, and up to 80 hours of unused sick time carried forward from one calendar year to the next - Additional paid time away may be requested to deal with critical or emergency issues for family members - Optional 10 paid days per full calendar year to volunteer For non-sales roles, employees are also eligible to earn annual bonuses subject to Cisco’s policies. Employees on sales plans earn performance-based incentive pay on top of their base salary, which is split between quota and non-quota components, subject to the applicable Cisco plan. For quota-based incentive pay, Cisco typically pays as follows: - .75% of incentive target for each 1% of revenue attainment up to 50% of quota; - 1.5% of incentive target for each 1% of attainment between 50% and 75%; - 1% of incentive target for each 1% of attainment between 75% and 100%; and - Once performance exceeds 100% attainment, incentive rates are at or above 1% for each 1% of attainment with no cap on incentive compensation. For non-quota-based sales performance elements such as strategic sales objectives, Cisco may pay 0% up to 125% of target. Cisco sales plans do not have a minimum threshold of performance for sales incentive compensation to be paid. The applicable full salary ranges for this position, by specific state, are listed below: New York City Metro Area: $225,000.00 - $374,100.00 Non-Metro New York state & Washington state: $208,600.00 - $330,000.00 * For quota-based sales roles on Cisco’s sales plan, the ranges provided in this posting include base pay and sales target incentive compensation combined. ** Employees in Illinois, whether exempt or non-exempt, will participate in a unique time off program to meet local requirements.

Role Description Seeking an engineer with experience in package layout and electrical analysis, focusing on power distribution and high-frequency signal integrity. - Develop and optimize package layouts - Perform PDN and signal integrity analysis - Run simulations and improve design performance - Collaborate with cross-functional engineering teams Qualifications - Degree in Electrical Engineering or related field - 10+ years of experience in package design and electrical analysis - Strong knowledge of power integrity and high-speed signal integrity - Hands-on experience with tools like Cadence APD, Cadence Clarity, Ansys HFSS, or similar (Siemens, Altium, etc.) - Experience with advanced packaging (2.5D/3D, flip-chip) Requirements - Work Status: US Citizen or Lawful Permanent Resident Benefits - 15 days of PTO per calendar year - 10 paid Holidays per calendar year - Comprehensive Medical Benefits: Company covers 80% of premiums for Employee and Dependents - Dental & Vision: Company covers 50% of premiums for Employee and Dependents - Voluntary Benefits: Life Insurance, FSA (Health and Dependent, Limited Purpose), HAS, and Gap Insurance - Employee Assistant Program (EAP) - 401k - Traditional & Roth - Life/AD&D and Long-Term Disability - Tuition reimbursement