TYLsemi

Role Description We are seeking an experienced Virtual Platform Development Lead to develop and own the virtual platform for next-generation SoCs targeting AI, HPC, and Networking applications. This role will leverage existing Virtualizer Platform tools to enable early architecture validation, hardware/software co-development, firmware development, and software bring-up well before silicon availability. The ideal candidate will have hands-on experience building complete SoC virtual platforms using a combination of RTL and SystemC/TLM models, and will work closely with architecture, design, verification, and firmware teams to accelerate product development and improve first-pass silicon success. - Develop and maintain complete SoC virtual platforms using Virtualizer Platform. - Integrate SoCs using a combination of RTL, SystemC/TLM models, processor models, memory models, and peripheral models. - Develop validation scenarios to verify architectural correctness, boot flows, data movement, and key system use cases. - Enable early firmware and software development before RTL and silicon availability. - Debug complex issues spanning architecture, RTL, SystemC models, firmware, and software. - Collaborate with Architecture, RTL, Design Verification, and Firmware teams to validate architectural intent and improve overall system quality. - Develop reusable methodologies, automation, and best practices for virtual platform development. Qualifications - Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field. - 8+ years of semiconductor design experience. - Strong hands-on experience with Synopsys Virtualizer. - Experience integrating complete SoCs using RTL and SystemC/TLM models. - Strong knowledge of C/C++, SystemC, and transaction-level modeling. - Good understanding of SoC architecture and hardware/software co-design. - Experience with high-speed interfaces such as PCIe, UCIe, and Ethernet. Knowledge of DDR/HBM memory interfaces is a plus. Key Attributes - Strong system-level thinking and debugging skills. - Passion for building scalable and reusable virtual platforms. - High ownership with a focus on quality and first-pass silicon success. - Excellent collaboration across architecture, design, verification, firmware, and software teams. Success Metrics - Early availability of virtual platforms for architecture validation and software development. - High-quality, reusable virtual platform infrastructure across multiple SoC programs. - Faster firmware and software readiness with reduced integration issues. - Improved first-pass silicon success through early system validation.

• Lead layout planning, floorplanning, and execution for analog and mixed-signal blocks on FinFET-based advanced nodes • Define and enforce analog layout techniques: matching, symmetry, common-centroid structures, guard-ringing, shielding, and parasitic-aware placement/routing for sensitive analog nets • Own integration guidelines between analog/mixed-signal blocks and digital logic • Identify and resolve advanced-node layout issues — including multi-patterning (MP) constraints, color-aware routing • Drive DRC/LVS/PERC/antenna closure and coordinate ECO layout cycles with design and verification teams • Manage layout schedules, milestones, and quality across internal teams and external layout vendors/subcontractors • Interface with packaging teams for integration on advanced packaging layout requirements • Define and drive layout methodology strategy, including use of APR tools and custom scripting/automation to improve efficiency • Mentor junior layout engineers and establish reusable layout methodologies, checklists, and best-practice documentation.

Role Description As Power Architecture Lead for PMIC, you will own the IVR architecture end-to-end — power conversion topology, digital control engine and analog subsystems. You will work directly with the Head of Engineering, digital architecture leads, and analog design team, and engage foundry partners and key customers at the architecture level. This role requires equal fluency in power electronics and mixed-signal IC design. You will define the architecture, validate the tradeoffs across topology, packaging, and thermal constraints, and drive execution through tape-out. What You’ll Do - Architecture & Definition - Define IVR architecture: multi-phase interleaved buck converter topology, phase count configurability, switching frequency selection, and efficiency targets across load conditions - Architect the digital control engine: per-phase duty cycle control, current balance, DVFS sequencing, and transient response optimization for AI workload dynamics - Define the control and telemetry interface - Establish power domain architecture for multi-domain compute targets: phase allocation, rail sequencing, and cross-domain coordination - Define input power spec, inrush management, and integration requirements for in-package passive components including integrated inductors - Mixed-Signal & Analog Oversight - Define requirements for analog subsystems: gate drivers, current sensing (DCR / integrated sense), on-chip thermal diodes, and oscillator / clock generation - Oversee integrated inductor evaluation and selection — saturation current, DCR, Q-factor, and co-design with converter switching frequency - Establish PVT corner strategy and margin targets across process, voltage, and temperature for all analog blocks - Drive analog-digital co-design: ensure digital control loop stability across all PVT corners with defined phase margin and gain margin targets - Define ESD and latch-up protection strategy for high-current power bumps - Implementation Oversight - Guide process node selection for Gen 1 and roadmap generations — evaluate tradeoffs between power density, analog capability, and cost - Lead IP evaluation for gate driver, ADC, and reference blocks; define custom vs. licensed IP strategy - Drive DFT strategy for power chiplet: stuck-at fault coverage, analog BIST for converter calibration, and production test requirements - Define packaging integration requirements - Customer & Ecosystem Engagement - Translate AI compute platform power delivery requirements into product specifications — engage customers at the architecture level to validate rail counts, current targets, and transient profiles - Interface with foundry partners on process capability, passive integration options, and packaging design rules - Support technical due diligence for strategic partnerships and customer evaluations - Roadmap & IP - Define the multi-generation architecture roadmap — establish a clear migration path from initial process node to advanced nodes with improved power density and packaging integration Qualifications - 15+ years in power IC architecture; 5+ years at Principal level or higher in a fabless, IDM, or PMIC-focused semiconductor environment - Deep expertise in multi-phase synchronous buck converter design — topology selection, loop compensation, stability analysis, and efficiency optimization across load - Mixed-signal IC design fluency: gate driver design, current sensing techniques, analog control loops, and ADC/DAC integration in CMOS processes - Hands-on experience with integrated passive components — on-chip or in-package inductors, capacitors, and their interaction with converter performance - Advanced packaging familiarity: flip-chip, 2.5D/3D integration, bump map design, and thermal/electrical co-design for power-dense applications - Experience driving power IC tape-outs from architecture definition through silicon bring-up and characterization - Proficiency in power converter simulation: SPICE-level transient analysis, AC loop stability, and PVT corner sweeps Good to Have - Experience with kilowatt-class power delivery for AI accelerators, GPUs, or high-performance CPUs is a big plus - Familiarity with in-package voltage regulator architectures (FIVR, LEGO-style VR, or substrate-embedded passives) - Background in PMBus / I2C / proprietary digital power management interfaces — experience migrating from legacy interfaces to die-to-die control fabric is a plus - Prior startup experience or comfort with early-stage technical ambiguity and fast-paced execution

• Define and drive the overall verification architecture for large-scale SoCs, ensuring scalability from IP → subsystem → full SoC level • Architect and develop reusable, modular, and portable verification platforms that can be leveraged across multiple chip programs • Establish methodologies for seamless reuse and portability, including Portable Stimulus (PSS)-based verification flows • Lead the development of high-performance, coverage-driven testbenches using industry-standard methodologies (e.g., UVM) • Drive multi-level verification strategies, enabling efficient scaling across: Block-level, Multi-block/subsystem level, Full-chip SoC level • Define and enforce verification quality metrics, coverage closure strategies, and sign-off criteria • Champion a “fail-fast” philosophy to detect issues early and improve overall design quality • Drive initiatives toward first-pass silicon success, minimizing escapes and post-silicon debug effort • Leverage AI/ML techniques and AI agents to: Automate testbench generation, Improve stimulus generation and coverage closure, Enhance regression efficiency and debug productivity, Enable intelligent verification QA and anomaly detection • Collaborate closely with design, architecture, physical design, and software teams to ensure alignment and early issue detection • Mentor and guide DV teams on best practices, methodology adoption, and architectural decisions.

• Own the end-to-end firmware/embedded-software architecture for TYLsemi chiplets • Define the firmware/hardware interface together with the Chip Architects for a seamless HW-to-SW handoff • On-die boot and secure boot, link sequencing, PCIe/CXL controller configuration • Define a unified flow for firmware development and DV test cases • Drive pre-silicon firmware and host-software development on emulation and virtual platforms • Stand up the firmware engineering infrastructure • Be the technical bridge between firmware/software and architecture • Set technical direction, roadmap, and clear subsystem ownership

Role Description We are looking for a highly motivated Senior Engineer – Physical Verification (PV) to join our Physical Design team. In this role, you will be responsible for driving block-level and full-chip physical verification signoff for advanced-node SoC designs. You will work closely with Physical Design, Layout, and Foundry teams to ensure high-quality and timely tapeouts. The role requires strong expertise in DRC/LVS methodologies, debugging complex violations, and improving PV automation flows. - Perform block-level and full-chip Physical Verification including DRC, LVS, ERC, antenna, and density checks - Drive PV closure and debug complex violations in collaboration with Physical Design and Layout teams - Execute hierarchical and flat verification methodologies for advanced-node designs - Develop and maintain PV runsets, automation scripts, and signoff flows - Analyze foundry rule decks and ensure design compliance with process requirements - Optimize verification runtime, memory usage, and turnaround time - Support tapeout activities and ensure clean signoff delivery Qualifications - Bachelor’s or Master’s degree in Electronics, Electrical Engineering, or VLSI-related discipline - 5+ years of hands-on experience in Physical Verification or Physical Design signoff - Strong understanding of DRC, LVS, ERC, antenna, and density verification concepts - Hands-on experience with Mentor Calibre and exposure to Synopsys ICV is a plus - Good understanding of CMOS fundamentals, layout effects, and advanced-node design rules - Proficiency in Tcl, Perl, Python, or Shell scripting for automation and flow development Requirements - Experience with advanced technology nodes such as 7nm, 5nm, or below - Exposure to FinFET technologies and multi-patterning design rules - Knowledge of reliability checks such as ESD, latch-up, and parasitic extraction/debug Success in This Role Looks Like - Achieving clean PV signoff with minimal iterations and timely tapeout support - Efficient debugging and closure of complex DRC/LVS violations - Improved verification productivity through automation and methodology enhancements - Strong collaboration across cross-functional teams leading to successful project execution

Role Description We are looking for a highly skilled Staff Physical Design Engineer to drive end-to-end physical implementation for advanced semiconductor designs across cutting-edge technology nodes. The ideal candidate will lead block/subsystem-level implementation activities, collaborate cross-functionally with RTL, STA, DFT, and CAD teams, and ensure high-quality tape-outs with strong focus on power, performance, and area (PPA). This role requires deep expertise in physical design methodologies, debugging complex issues, and mentoring junior engineers. - Lead full-chip or block-level physical design implementation from floorplanning to GDS signoff. - Drive floorplanning, power planning, placement, CTS, routing, optimization, and physical verification closure. - Analyze and optimize timing, congestion, IR drop, EM, and power for advanced technology nodes. - Collaborate with RTL, DFT, STA, package, and CAD teams to resolve implementation and signoff challenges. - Develop and improve physical design flows, automation scripts, and methodology enhancements. - Support tape-out activities and ensure design signoff quality across all implementation stages. - Mentor junior engineers and contribute to technical reviews and best practices. Qualifications - Bachelor’s or Master’s degree in Electronics, Electrical Engineering, VLSI, or related field. - 8+ years of hands-on experience in ASIC/SOC physical design implementation. - Strong expertise in industry-standard EDA tools such as Cadence Innovus, Synopsys ICC2, PrimeTime, and StarRC. - Solid understanding of timing closure, low-power design techniques, signal integrity, IR/EM analysis, and physical verification. - Experience working on advanced technology nodes (7nm/5nm/3nm preferred). - Strong scripting skills in Tcl, Perl, or Python for automation and flow enhancement. - Excellent debugging, problem-solving, communication, and stakeholder collaboration skills. Requirements - Experience with hierarchical and top-level SOC integration. - Exposure to ML/AI-based design optimization methodologies. - Knowledge of package-aware implementation and multi-die/chiplet architectures. Success in This Role Looks Like - Consistent delivery of high-quality physical design milestones with minimal schedule impact. - Successful closure of timing, power, area, and reliability metrics for complex SOC designs. - Proactive identification and resolution of implementation bottlenecks and signoff risks. - Positive contribution to team productivity, methodology improvements, and mentoring initiatives.

Role Description We are seeking a highly experienced Principal Physical Design Engineer to lead complex ASIC/SOC physical implementation activities across advanced technology nodes. The role requires deep expertise in full-chip and block-level implementation, technical leadership in achieving best-in-class PPA (Power, Performance, Area), and ownership of high-quality tape-outs. The ideal candidate will collaborate closely with cross-functional teams and drive methodology improvements, design closure strategies, and mentoring initiatives. What You’ll Do - Lead end-to-end physical design implementation from floorplanning through GDSII signoff for complex SOCs and subsystems. - Define and drive implementation strategies for timing, congestion, power, area, IR/EM, and signal integrity closure. - Collaborate with RTL, STA, DFT, Packaging, and CAD teams to resolve complex design and integration challenges. - Own physical signoff including timing, DRC, LVS, IR drop, EM, and reliability analysis. - Drive advanced node implementation methodologies and optimize design QoR across multiple projects. - Develop and improve automation scripts, flows, and reusable methodologies for implementation efficiency. - Lead technical reviews, mentor junior engineers, and provide project execution guidance. - Support tape-out activities and customer/escalation debugging when required. Qualifications - Bachelor’s or Master’s degree in Electronics, Electrical Engineering, VLSI, or related field. - 12+ years of hands-on experience in ASIC/SOC physical design implementation. - Strong expertise in floorplanning, placement, CTS, routing, timing closure, and physical verification. - Hands-on experience with EDA tools such as Cadence Innovus, Synopsys ICC2, PrimeTime, StarRC, and Voltus/RedHawk. - Deep understanding of advanced node challenges including low-power design, SI, IR/EM, and variability analysis. - Proven experience delivering successful tape-outs at advanced technology nodes (7nm/5nm/3nm preferred). - Strong scripting and automation skills using Tcl, Python, Perl, or Shell. - Excellent problem-solving, leadership, communication, and stakeholder management skills. Requirements - Experience with hierarchical SOC integration and top-level implementation. - Exposure to 3D IC, chiplet, or package-aware implementation methodologies. - Experience in AI/ML-driven EDA optimization techniques. Success in This Role Looks Like - Successful delivery of complex SOC designs meeting aggressive PPA and schedule targets. - Consistent achievement of implementation and signoff closure with high-quality tape-outs. - Improved team productivity through methodology enhancements and automation. - Strong technical leadership, mentoring impact, and cross-functional collaboration.

• Lead end-to-end STA and timing signoff activities for full-chip and subsystem-level designs. • Drive timing closure across setup, hold, SI, noise, crosstalk, IR-aware timing, and MMMC scenarios. • Define timing constraints, validate SDCs, and ensure robust timing methodology execution. • Collaborate closely with RTL, Physical Design, DFT, CTS, and CAD teams to achieve timing convergence. • Analyze and resolve complex timing violations and critical path bottlenecks. • Support ECO implementation and signoff verification for advanced node tape-outs. • Develop and improve automation flows, scripts, timing dashboards, and methodology enhancements. • Mentor engineers and lead technical reviews for timing architecture and signoff readiness.

Role Description We are seeking a highly skilled Staff Engineer – Physical Verification (PV) to lead physical verification and signoff activities for complex ASIC/SOC designs across advanced technology nodes. The ideal candidate will drive DRC, LVS, ERC, ANTENNA, and reliability verification closure while collaborating closely with Physical Design, Layout, Foundry, and CAD teams to enable high-quality and timely tape-outs. This role requires deep expertise in signoff methodologies, debugging complex violations, and driving automation and process improvements. - Lead block-level and full-chip physical verification and signoff activities for advanced SOC designs. - Drive DRC, LVS, ERC, ANTENNA, density, and reliability closure using industry-standard signoff methodologies. - Debug and resolve complex physical verification issues in collaboration with Physical Design, Custom Layout, and Foundry teams. - Develop and maintain scalable PV automation flows, rule decks, and regression infrastructure. - Analyze and resolve manufacturing and reliability challenges including EM/IR, latch-up, and ESD-related issues. - Support hierarchical verification, tape-out execution, and final GDS signoff deliverables. - Collaborate with CAD and EDA vendors for tool qualification, flow enhancement, and issue resolution. - Mentor junior engineers and contribute to methodology development and best practices. Qualifications - Bachelor’s or Master’s degree in Electronics, Electrical Engineering, VLSI, or related field. - 10+ years of experience in physical verification and signoff for ASIC/SOC designs. - Strong expertise in DRC, LVS, ERC, ANTENNA, density checks, and debugging methodologies. - Hands-on experience with industry-standard tools such as Calibre, ICV, Pegasus, or equivalent verification platforms. - Good understanding of physical design flow, layout concepts, process technologies, and manufacturing requirements. - Experience with advanced technology nodes including 7nm/5nm/3nm designs. - Strong scripting and automation skills using Tcl, Python, Perl, or Shell. - Excellent analytical, debugging, communication, and technical leadership skills. Requirements - Experience with reliability verification including EMIR, ESD, and latch-up analysis. - Exposure to chiplet-based designs, 3D ICs, and advanced packaging technologies. - Knowledge of foundry tape-out processes and signoff qualification requirements. Success in This Role Looks Like - Successful closure of physical verification signoff for complex SOC tape-outs with high quality. - Fast and efficient resolution of physical verification and manufacturing violations. - Improved PV methodology scalability, automation, and execution efficiency. - Strong technical leadership and mentoring contributions across engineering teams.