Delos Data

• Design and implement RTL for complex digital subsystems using Verilog/SystemVerilog • Translate architectural specifications into clean, efficient, and scalable microarchitectures • Collaborate with architecture, verification, and physical design teams to ensure design correctness and closure • Develop high-quality, reusable RTL with strong coding standards and documentation • Perform linting, CDC analysis, and ensure synthesis readiness of designs • Support integration and debug of RTL in simulation and early silicon environments • Participate in design reviews and provide technical input on architecture and implementation tradeoffs • Work with verification teams to ensure comprehensive functional coverage • Assist in timing closure and support backend teams as needed • Contribute to continuous improvement of design methodologies, flows, and tools

• Develop, implement, and maintain RTL verification environments using UVM or equivalent methodologies • Create and execute coverage-driven verification plans aligned with design specifications • Use EDA DFT tools (e.g., TestMax, Tessent) to create and run recommended pre-silicon test cases for MBIST and scan fabric inserted by those tools • Develop directed test cases for other (non-vendor-supplied) DFT logic to validate functionality and identify corner cases • Assist in verifying ATPG patterns, especially at SOC level, along with manufacturing reset sequences • Analyze simulation results, debug complex verification and design issues, and perform root-cause analysis in collaboration with DFT design engineers • Implement and track functional and code coverage, driving verification to closure • Develop reusable verification components and write SystemVerilog Assertions (SVA) • Participate in design and verification reviews, providing input on design testability, correctness, and optimization • Automate regression testing and enhance verification infrastructure using Python and scripting • Contribute to continuous improvement of verification processes, tools, and methodologies • Along with the DFT designers, help support post-silicon test bring-up debug

• Design, develop, and maintain a robust automated testing framework from the ground up that supports distributed AI training and inference workloads. • Develop complex test plans that go beyond unit tests, focusing on end-to-end system integration, stress testing, and hardware-software boundary conditions. • Partner closely with System Engineers to debug deep-seated issues in distributed clusters, using telemetry and profiling tools to identify bottlenecks.

• Define the technical roadmap for server hardware platforms and advanced package technologies (e.g., 2.5D/3D IC, chiplets, system-in-package). • Oversee end-to-end system design, including high-speed board-level hardware, ASIC packaging, SI/PI simulations, and PCB layout. • Lead and mentor a multidisciplinary team of electrical, mechanical, and package engineers. • Partner with silicon design, firmware, software, and manufacturing teams to ensure integration and manufacturability (DFM/DFT). • Interface with OSAT and ODM partners to drive packaging technologies, prototype builds, and manufacturing quality. • Guide system bring-up, validation, and debug, including thermal and power management. • Own the full hardware lifecycle from concept through volume production, including schedules and budgets.

• Translate high-level system requirements into FPGA architectural and micro-architectural specifications • Develop robust, clean, and maintainable RTL code using VHDL, Verilog, and SystemVerilog • Create and utilize simulation testbenches using tools such as XCelium and Vivado to verify functionality and performance • Perform synthesis, place-and-route, and static timing analysis using Xilinx tools (Vivado, ISE) • Optimize designs for performance, power, and area (PPA) • Bring up FPGAs on custom PCBs and debug using oscilloscopes, logic analyzers, and on-chip debugging tools (Vivado Logic Analyzer) • Develop scripts to update and download FPGA clusters in live server environments • Collaborate with hardware, software, systems, and verification engineers to ensure system integration and validation • Create and maintain design specifications, test plans, and test results documentation • Build and maintain FPGA software environments using Vitis, including toolchains, reference drivers, and processor core environments

• Collaborate across the stack to influence the design of our foundational technology, ensuring it meets the needs of next-generation AI models. • Identify and resolve performance bottlenecks in distributed training and inference workloads through deep-dive analysis of the software-hardware interface. • Conduct rigorous performance benchmarking and characterization on multi-node clusters.

• Package Development: Select and design optimal multi-die IC package types considering electrical performance, cost, and manufacturability. • Signal Integrity (SI) Analysis: Perform pre- and post-layout simulations (e.g., eye diagrams, crosstalk) for high-speed interfaces (UCIe, D2D, high-speed serdes). • Power Integrity (PI) Analysis: Model and simulate Power Delivery Networks (PDN) for low-voltage, high-current supplies, including AC/DC analysis and IR drop. • Modeling & Simulation: Develop accurate simulation models (S-parameters, IBIS-AMI) for packages, PCBs, and sockets. • Cross-Functional Collaboration: Work with IC design, physical design, board layout, and marketing teams to define requirements and resolve issues. • Layout Review: Guide PCB/package layout, reviewing stack-ups, trace routing, and component placement for optimal SI/PI performance. • Lab Validation: Support hardware bring-up, debug, and correlation between simulation/models and physical measurements. • Technology Development: Research and implement new SI/PI techniques and tools for next-generation products.

• Lead the creation of Architectural Design Specifications (ADS) and Micro-architecture Specifications (MAS) for complex ASICs. • Develop high-level performance models (using SystemC/TLM, C++, or Python) to analyze workload behaviors and validate architectural assumptions. • Optimize chip-level and block-level architecture to meet stringent power, performance, and area goals. • Define high-speed interconnect fabric, memory subsystems (DDR/HBM), and IO protocols (PCIe, CXL, UCIe). • Partner with RTL design, verification, physical design, firmware, and software teams to ensure seamless implementation and validation. • Drive architectural trade-off studies and lead design reviews. • Define advanced power management strategies including DVFS, power domains, and clock gating. • Mentor junior engineers and contribute to technical leadership across the organization.

• Develop, implement, and maintain RTL verification environments using UVM or equivalent methodologies • Create and execute coverage-driven verification plans aligned with design specifications • Develop directed and constrained-random test cases and sequences to validate functionality and identify corner cases • Analyze simulation results, debug complex verification and design issues, and perform root-cause analysis in collaboration with RTL design engineers • Implement and track functional and code coverage, driving verification to closure • Develop reusable verification components and write SystemVerilog Assertions (SVA) • Participate in design and verification reviews, providing input on design testability, correctness, and optimization • Automate regression testing and enhance verification infrastructure using Python and scripting • Contribute to continuous improvement of verification processes, tools, and methodologies