RTL Design Engineer
Location
United States
Posted
18 days ago
Salary
$160K - $220K / year
Seniority
Senior
Job Description
RTL Design Engineer
Delos Data
• Design and implement RTL for complex digital subsystems using Verilog/SystemVerilog • Translate architectural specifications into clean, efficient, and scalable microarchitectures • Collaborate with architecture, verification, and physical design teams to ensure design correctness and closure • Develop high-quality, reusable RTL with strong coding standards and documentation • Perform linting, CDC analysis, and ensure synthesis readiness of designs • Support integration and debug of RTL in simulation and early silicon environments • Participate in design reviews and provide technical input on architecture and implementation tradeoffs • Work with verification teams to ensure comprehensive functional coverage • Assist in timing closure and support backend teams as needed • Contribute to continuous improvement of design methodologies, flows, and tools
Job Requirements
- Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field
- 5+ years of experience in RTL design
- Strong hands-on experience with Verilog/SystemVerilog
- Solid understanding of synchronous digital design and microarchitecture principles
- Experience with simulation and debug tools (e.g., VCS, Questa, Verdi, DVE)
- Familiarity with synthesis, timing, and physical design constraints
- Strong analytical and problem-solving skills
- Clear written and verbal communication skills for cross-functional collaboration
- High attention to detail and ability to deliver high-quality design outcomes
- Ability to work independently and manage tasks to completion
Benefits
- meaningful equity
- health insurance
- 401(k)
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