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Ciena

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Principal SerDes System – DSP Design Engineer

Mechanical EngineerMechanical EngineerFull TimeRemoteLeadTeam 5,001-10,000Since 1985H1B SponsorCompany SiteLinkedIn

Location

Canada

Posted

121 days ago

Salary

$126.1K - $201.5K / year

Seniority

Lead

Postgraduate Degree8 yrs expEnglishDACPython

Job Description

Principal SerDes System – DSP Design Engineer

Ciena

• Lead the architecture, design, and validation of high-speed serial transceivers across electrical and optical domains • Leverage expertise in systems engineering, control theory, DSP algorithms, and modeling to develop cutting-edge serial electrical/optical-IMDD transceiver solutions • Perform system-level evaluation, modeling, and performance analysis of SerDes transceiver solutions including impairments and mitigation techniques • Develop algorithms and architectures for adaptive equalization, maximum likelihood sequence detection (MLSD), and timing recovery algorithms • Integrate control theory and advanced DSP designs into feasible hardware implementations • Collaborate with cross-functional teams (analog design, ASIC design, electro-optical hardware, firmware) to optimize SerDes performance in end-to-end systems • Conduct design trade-offs to meet stringent performance, power, and area targets • Analyze channel models, analog circuits impairments (DAC, ADC, AFE, …) and system constraints to determine system level margin and FEC (forward error correction) performance and optimize system margin • Document design specifications, system performance results, and contribute to IP generation and innovation roadmaps

Job Requirements

  • Advanced expertise in electrical SerDes DSP design and implementation
  • Proven experience in SerDes system-level evaluation, modeling, and simulation
  • Strong proficiency in control theory and digital signal processing (DSP) applied to high-speed communication systems
  • Familiarity with optical IMDD (Intensity Modulation Direct Detection) systems
  • Deep understanding of adaptive equalization techniques for high-speed links
  • Proficiency with maximum likelihood sequence detection (MLSD) approaches
  • Expertise in timing recovery schemes in high-speed serial links
  • Practical knowledge of FEC performance modeling and system-level performance optimization
  • Experience with MATLAB, Python, or C/C++ for algorithm design and simulation
  • Strong problem-solving skills and ability to work across hardware/software boundaries
  • Ph.D. in Electrical Engineering with background in digital communications and signal processing
  • 8+ years of experience in high-speed serial link or communication system design

Benefits

  • medical, dental, and vision plans
  • participation in 401(K) (USA) & DCPP (Canada) with company matching
  • Employee Stock Purchase Program (ESPP)
  • Employee Assistance Program (EAP)
  • company-paid holidays
  • paid sick leave
  • vacation time
  • comply with all applicable laws regarding Paid Family Leave and other leaves of absence

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