Niobium Microsystems

• Develop Niobium’s R&D business strategy for federal research, development and transition funding. • Develop and execute capture and business development strategy for federal research and development and technology transition funding. • Analyze commercial customer needs utilizing market research, competitive intelligence, and knowledge of industry trends. • Strategically align Niobium’s R&D technologies Technical Readiness Levels (TRL) roadmap with government mission and commercial opportunities. • Collaborate with the Niobium Engineering and Operations team members by providing regular updates and partnering on forecasts, resource planning, and existing technology roadmap progress. • Build relationships with potential business partners and customers to build a network of partners to further Niobium’s strategic business development pursuits. • Collaborate internally and externally to qualify leads, create quality proposals, and win new work. • Own the execution of all proposal stages and all aspects of communication to all stakeholders. • Manage capture resources effectively including budgets, optimizing utilization and ensuring alignment with financial targets.

• Lead the Porting Effort: Take Ownership of porting our existing ASIC RTL to the AMD Alveo V80 • Ensure the design is scalable, parameterizable, and optimized for the Versal HBM architecture • Architect the RTL to support a unified codebase for both FPGA and ASIC targets • Implement abstractions for memory, clocking, and resets that allow for seamless migration between programmable logic and custom silicon • Optimize the CKKS FHE data path, including: NTT, KeySwitching, and Base Conversion to exceed the performance of state-of-the-art GPU implementations • Use the FPGA platform as an iterative testbed to validate code and architectural improvements for future generations of our hardware • Resolve the current team's challenges with debugging and toolchain experience • Implement robust hardware debugging strategies using Vivado Hardware Manager, ILA cores, and Vitis emulation flows • Take full responsibility for achieving timing closure on high density Versal designs • Optimize the design for resource utilization (LUTs, DSPs, URAM) and power efficiency • Architect and tune the Versal Programmable Network-on-Chip (NoC) to prioritize high bandwidth data movement between HBM2e and the PL fabric • Initially lead backend and frontend engineering efforts, then assist in hiring and technical leadership of a multi-disciplinary team (Backend, Frontend, DevOps, Customer Support) to support growth from 5 pilot users to thousands of concurrent users • Ensure the infrastructure meets enterprise-grade standards from day one, preparing the platform for HIPAA, SOC2, and GDPR compliance

• Build the Niobium Cloud Console—the single pane of glass where data scientists and security architects provision hardware, manage encryption keys, and visualize the performance gains of our proprietary silicon for fully encrypted compute • A complex, single-page application (SPA) that serves as the mission control for our users • Build flows for account creation, billing management, and hardware fleet management • Implement heavy data visualization (using D3, Recharts, or similar) to compare execution speeds in real-time • Integrate WebSocket-based terminal emulators (like xterm.js) into the browser • Build the interface for our "Quick Start" marketplace, where users can deploy pre-configured FHE applications with a single click • Own the frontend codebase (likely React/TypeScript) from init to production • Work closely with the Backend Lead to consume REST/gRPC APIs that control physical infrastructure • Implement secure workflows for key generation • Collaborate with our Product and Design teams (who will provide visual assets and UX wireframes) • Support customers and partners via ticketing systems and other support channels

• Build the control plane that automatically provisions client-server environments. • Create the internal APIs that allow our software to treat a room full of FPGAs as a scalable cloud resource. • Design and implement the public-facing APIs that power our Command Line Interface (CLI) and Web Console. • Build secure pipelines (using S3/GCS protocols) that allow customers to stream encrypted data from their existing cloud buckets into the Niobium Cloud. • Design high-throughput, low-latency microservices (likely in Go, Rust, or Python). • Deeply integrate with Terraform, Kubernetes, and Ansible to automate the deployment of the entire cloud stack. • Implement rigorous authentication and authorization (OAuth/OIDC) protocols. • Optimize hardware performance. • May be required to work on-site at data centers during deployments, expansions, or critical break-fix situations. • Support customers and partners via ticketing systems and other support channels, with a focus on problem-solving and customer success. • Occasional on-call availability may be required.

• End-to-End Physical Implementation Leadership • Own and lead all physical design activities from RTL handoff, floorplanning, and PnR through final GDSII delivery • Define execution strategy, schedules, design methodology, and quality checkpoints for the entire physical design flow • Architect and execute floorplanning strategies for large, hierarchical SoCs • Collaborate with Architecture and RTL teams to ensure physical feasibility, timing closure readiness, and area/power targets • Lead block-level and top-level PnR using industry standard EDA tools (Cadence, Synopsys) • Drive timing convergence across corners, modes, voltage domains, and operating conditions • Own optimization for PPA (Power, Performance, Area), congestion mitigation, and physical integrity • Implement CTS and drive skew, latency, and clock power optimization • Lead IR/EM sign-off strategy, thermal analysis, and full chip physical verification (DRC/LVS/ERC) • Partner with DFT and PD teams to ensure scan insertion, BIST structures, and test modes are physically robust and timing clean • Work with Packaging and SI teams on bump planning, floorplan constraints, and package-aware timing • Set physical design quality standards, conduct design reviews, and ensure flawless execution through tapeout • Provide technical leadership to a team of junior and mid-level physical designers • Mentor, coach, and guide engineers in methodology, debug, and best practices • Champion continuous improvement across flows, scripts, and design methodology