This description is a summary of our understanding of the job description. Click on 'Apply' button to find out more. Role Description Revamp is seeking a Design Engineering Intern to support utility-scale solar and battery energy storage (BESS) projects. This is a drafting-intensive role where strong AutoCAD proficiency is the most important qualification. - Work alongside experienced engineers to develop and update project layouts - Apply design markups - Contribute to real-world renewable energy projects that directly support the energy transition Intern Program Details - Twelve-week full-time summer program, remote or in-office if local - Approximately 40 hours per week during the summer term - Schedule flexibility may be available to accommodate academic calendars - Interns work under the direction of a designated manager - Interns may be evaluated for future full-time employment opportunities upon graduation Duties & Responsibilities Engineering & Technical Responsibilities - Prepare and modify engineering drawings using AutoCAD with a high degree of accuracy and efficiency - Develop and update project layouts and drawing sets for PV and BESS projects - Incorporate redlines and markups from senior engineers into construction documents - Organize and maintain drawing files in accordance with company standards - Support basic design calculations, documentation, and quantity takeoffs as assigned - Apply foundational engineering principles learned through academic coursework - Develop and apply basic programming solutions (e.g., Excel formulas/VBA, AutoCAD scripting, or similar tools) to improve drafting efficiency, automate repetitive tasks, and enhance internal design workflows - Perform routine technical work under close supervision Collaboration & Team Support - Manage time effectively across assigned drafting and design tasks - Coordinate with engineers and project team members to clarify drawing requirements - Participate in internal project meetings as needed - Receive direction on technical challenges and incorporate feedback into revisions - Perform additional duties as assigned or directed Additional Responsibilities - Perform essential duties including meeting project deliverables and deadlines - Perform additional related duties as assigned or directed Qualifications - Actively enrolled in a Bachelor's or Master's degree program in Engineering or a closely related technical field - Prior exposure to solar energy systems (coursework or prior internship) - Demonstrated proficiency in AutoCAD; ability to efficiently create and modify engineering drawings - Strong attention to detail and drawing accuracy - Ability to interpret engineering markups and redlines - Foundational understanding of engineering design principles - Strong written and verbal communication skills - Ability to manage assigned tasks independently while working under supervision Requirements - Prior internship experience in renewable energy, solar, engineering, or related infrastructure projects (preferred) - Experience with drafting for construction or engineering design projects (preferred) - Basic coding experience in Python, VBA, or Autodesk AutoLISP routines (not required) - Exposure to renewable energy system components such as modules, racking, inverters, or BESS equipment (preferred) Benefits - Competitive hourly compensation - Exposure to large-scale renewable energy engineering operations - Mentorship from experienced engineers - Opportunity to contribute to projects supporting the energy transition

This description is a summary of our understanding of the job description. Click on 'Apply' button to find out more. Role Description We are seeking a highly skilled Principal Digital ASIC Design Engineer to lead the design and implementation of digital subsystems for advanced wireless SoCs. You will be part of a collaborative design team developing state-of-the-art mixed-signal SoCs to be hosted on some of the largest, most powerful, rapidly designed and rapidly manufactured satellites ever deployed in space. In your first 6 months, you will architect, develop, and implement new SoC sub-systems for satellite communications and beyond. In your first two years, you will have flown your sub-system in space and developed cutting-edge mixed-signal SoCs. - Own the architecture, microarchitecture, RTL implementation, and integration of key digital blocks in wireless SoCs. - Collaborate with system architects to translate high-level DSP algorithms into efficient hardware implementations. - Drive end-to-end development of DSP systems (e.g., filters, beamformers, FFT/IFFT engines). - Convert chip specifications into RTL using internal IPs and external IPs. - Design and develop RTL for interfaces, power management, clocking, reset, test & debug. - Partner with analog/mixed-signal teams to define digital-analog interfaces, calibration engines, and control logic. - Optimize designs for power, performance, and area (PPA) and support timing closure through synthesis and backend collaboration. - Lead or contribute to verification planning and validation of complex digital subsystems. - Participate in chip bring-up and lab validation of complex digital subsystems. - Support your product through production and spaceflight. - Act as a technical leader and subject-matter expert, helping to teach, grow, and mentor others in the team. Qualifications - B.S. or M.S. in Electrical Engineering, Computer Engineering, or related field. - 10+ years of relevant industry experience in digital ASIC design, with significant ownership of complex subsystems. - Proficiency in RTL design (SystemVerilog or Verilog), synthesis, and linting tools. - Experience in micro-architecture definition from architecture guideline and model analysis. - Experience in closing full-chip and subsystem timing working with synthesis and static analysis teams. - Experience with DFT tools for scan and BIST insertion. - Solid understanding of SoC design flows including clock/power domain crossing, timing constraints, and formal verification. - Experience developing and integrating DSP blocks for wireless communication (e.g. OFDM, MIMO, channel estimation, DFE, etc.). - Strong experience with EDA tools for design, synthesis, static timing analysis, and power analysis (e.g. Synopsys, Cadence, Siemens tools). - Strong debugging, problem-solving, and communication skills. Requirements - Prior experience in wireless SoC development (e.g. cellular, Wi-Fi, satellite, or mmWave systems) and successful tapeouts in advanced design nodes. - Design experience in datapath, flow control, arbitration, FIFO, DMA, IOMMU, SoC bus architecture, ARM’s AXI/AHB bus architecture & protocols, serial interfaces such as SPI, I3C, UART. - Familiarity with DSP algorithm modeling (MATLAB, Python, or C++) and converting models into RTL. - Experience working with FEC, baseband PHYs, or digital beamforming architectures. - Knowledge of digital calibration and control of RF/mixed-signal front ends. - Exposure to hardware-software co-design and embedded process integration. - Experience working in cross-functional, geographically distributed teams. Benefits - Base salary range for this role is $190,000 – $285,000 + equity in the company. - Salary will be based on several factors including, but not limited to: knowledge and skills, education, and experience level. - Comprehensive benefits package including paid time off, medical/dental/vision coverage, life insurance, paid parental leave, and many other perks.

This description is a summary of our understanding of the job description. Click on 'Apply' button to find out more. Role Description - Assist with silicon bring-up - Contribute to all areas of SoC design, verification, and implementation - Design, implement and integrate complex SoC blocks - Develop block-level test cases to deliver fully functional designs - Develop micro-architecture specifications based on the SoC requirements - Develop synthesis constraints and resolve timing issues - Identify and resolve RTL and Gate-Level Simulation (GLS) failures at block and chip level - Participate in architectural feasibility studies - Participate in ECO implementation - Projects range from integrating third party IPs to designing complex systems - Resolve Lint, CDC, and DFT related issues Qualifications - BSEE/MSEE with 15+ years of SoC design/architecture experience - Clock domain crossing methodologies - Experience with RISC-V architecture - Logic synthesis and static timing analysis - Modeling SoC architectures with FPGAs - RTL Design including HVLs and HDLs (SystemVerilog, Verilog) - Scripting languages such as Python, Perl, Tcl, shell, etc. - SoC design flow including chip-level design, block/IP design and behavioral modeling - Strong familiarity with EDA tools - Strong problem solving and debugging capabilities - Third Party IP Integration experience - Working knowledge of PCIe and DDR - Working knowledge of standard bus protocols such as AXI/AMBA/TileLink - Working knowledge of SoC design with Chisel (plus) - Asynchronous logic design (plus) Benefits - Competitive salary scaled based on experience - Bonus - Stock - Employer paid health care - Employer contribution to health savings account - Flexible time off - Flexible work location with remote options - 401K employer match

K2 is building the largest and highest-power satellites ever flown, unlocking performance levels previously out of reach across every orbit. Backed by $450M from leading investors including Altimeter Capital, Redpoint Ventures, T. Rowe Price, Lightspeed Venture Partners, Alpine Space Ventures, and others – with an additional $500M in signed contracts across commercial and US government customers – we’re mass-producing the highest-power satellite platforms ever built for missions from LEO to deep space.  The rise of heavy-lift launch vehicles is shifting the industry from an era of mass constraint to one of mass abundance, and we believe this new era demands a fundamentally different class of spacecraft. Engineered to survive the harshest radiation environments and to fully capitalize on today’s and tomorrow’s massive rockets, K2 satellites deliver unmatched capability at constellation scale and across multiple orbits.  With multiple launches planned through 2026 and 2027, we're Building Bigger to develop the solar system and become a Kardashev Type II (K2) civilization. If you are a motivated individual who thrives in a fast-paced environment and you're excited about contributing to the success of a groundbreaking Series C space startup, we’d love for you to apply.  The Role We are seeking a highly skilled Lead Digital ASIC Engineer to drive the design and implementation of digital subsystems for advanced wireless SoCs along with managing a team of ASIC design engineers. You will work as part of a collaborative design team developing state-of-the-art mixed-signal SoCs to be hosted on some of the largest, most powerful, rapidly designed and rapidly manufactured satellites ever deployed in space. In this role, you will take ownership of significant digital blocks, lead technical initiatives, and contribute to the development of cutting-edge communication systems for space applications. Responsibilities - Lead and manage a team of digital design engineers, providing technical mentorship, career development, and performance management. - Manage development schedules, track deliverables, and report status to senior leadership and cross-functional teams. - Contribute to design and implementation of microarchitecture and RTL for key digital blocks in wireless SoCs, including DSP systems, interfaces, and control logic. - Collaborate with system architects to translate high-level DSP algorithms and chip specifications into efficient hardware implementations. - Develop RTL for complex digital subsystems such as filters, beamformers, FFT/IFFT engines, and digital front-ends. - Contribute to design and integration of digital blocks for interfaces, power management, clocking, reset, test, and debug infrastructure. - Work with analog/mixed-signal teams to define and implement digital-analog interfaces, calibration engines, and control logic. - Optimize designs for power, performance, and area (PPA) while meeting timing, area, and power constraints. - Collaborate with synthesis and backend teams to achieve timing closure and resolve design issues. - Contribute to verification planning and work closely with verification teams to validate complex digital subsystems. - Participate in chip bring-up and lab validation activities for digital subsystems. - Support products through production and spaceflight operations. - Mentor junior engineers and contribute to team technical growth and best practices. Qualifications - B.S. or M.S. in Electrical Engineering, Computer Engineering, or related field. - 10+ years of industry experience in digital ASIC design with ownership of complex digital blocks or subsystems. - 3+ years of experience leading ASIC design teams or projects, including mentoring engineers and managing deliverables. - Strong proficiency in RTL design using SystemVerilog or Verilog, with experience in synthesis and linting tools. - Experience in microarchitecture definition and implementation based on architectural guidelines and analysis. - Hands-on experience with timing closure, working effectively with synthesis and static timing analysis teams. - Familiarity with DFT concepts and tools for scan and BIST insertion. - Solid understanding of SoC design flows including clock/power domain crossing, timing constraints, and verification methodologies. - Experience with DSP blocks for wireless communication systems (e.g., OFDM, MIMO, channel estimation, DFE). - Proficiency with industry-standard EDA tools for design, synthesis, static timing analysis, and power analysis (e.g., Synopsys, Cadence, Siemens tools). - Strong debugging, problem-solving, and communication skills with ability to work effectively in cross-functional teams. Nice to Have - Experience in wireless SoC development (e.g., cellular, Wi-Fi, satellite, or mmWave systems) with successful tapeouts. - Design experience with datapath architectures, flow control, arbitration, FIFO, DMA, IOMMU, and SoC bus architectures. - Experience with ARM's AXI/AHB bus architectures and protocols, and serial interfaces such as SPI, I3C, UART. - Familiarity with DSP algorithm modeling using MATLAB, Python, or C++ and converting models into RTL implementations. - Experience working with FEC, baseband PHYs, or digital beamforming architectures. - Knowledge of digital calibration and control of RF/mixed-signal front ends. - Exposure to hardware-software co-design and embedded processor integration. - Experience working in fast-paced startup or cross-functional, geographically distributed teams. Compensation and Benefits: - Base salary range for this role is $200,000 – $300,000 + equity in the company - Salary will be based on several factors including, but not limited to: knowledge and skills, education, and experience level - Comprehensive benefits package including paid time off, medical/dental/vision/ coverage, life insurance, paid parental leave, and many other perks If you don’t meet 100% of the preferred skills and experience, we encourage you to still apply! Building a spacecraft unlike any other requires a team unlike any other and non-traditional career twists and turns are encouraged! If you need a reasonable accommodation as part of your application for employment or interviews with us, please let us know. Export Compliance As defined in the ITAR, “U.S. Persons” include U.S. citizens, lawful permanent residents (i.e., Green Card holders), and certain protected individuals (e.g., refugees/asylees, American Samoans). Please consult with a knowledgeable advisor if you are unsure whether you are a “U.S. Person.” The person hired for this role will have access to information and items controlled by U.S. export control regulations, including the export control regulations outlined in the International Traffic in Arms Regulation (ITAR). The person hired for this role must therefore either be a “U.S. person” as defined by 22 C.F.R. § 120.15 or otherwise eligible for a federally issued export control license. Equal Opportunity K2 Space is an Equal Opportunity Employer; employment with K2 Space is governed on the basis of merit, competence and qualifications and will not be influenced in any manner by race, color, religion, gender, national origin/ethnicity, veteran status, disability status, age, sexual orientation, gender identity, marital status, mental or physical disability or any other legally protected status.