• lead system-level architecture planning for Server/AI platforms, including product configuration definition, functional partitioning, and mechanical/thermal/power/cooling feasibility alignment • drive the definition of system requirements, interface specifications, and early configuration options (e.g., GPU, accelerator, storage, and compute servers) • conduct architectural trade-off analysis balancing performance, cost, power, scalability, and manufacturability • collaborate with EE, thermal, mechanical, BMC, and firmware architects to form a complete product-level concept package • work with Architecture and BU teams to evaluate RFQ/RFI requirements and generate competitive architecture proposals • define and propose system topologies, mechanical footprints, airflow design, I/O mappings, and cabling options • interface with customers and internal stakeholders to align design intent and value proposition during the concept phase • present and document concept proposals that include block diagrams, design strategy, trade-off summary, and risk evaluation • stay up to date with Open Compute (OCP), Computer Express Link (CXL) or Open BMC • evaluate and integrate technology enablers such as PCIe Gen5/6, high-efficiency power stages, and new materials • participate in roadmap planning with BU/CTO to ensure platform reusability and alignment with future-generation technologies • define how electrical, mechanical, thermal, and firmware domains interact to support functional and performance goals • coordinate platform-level integration strategies including MB placement, airflow optimization, and system serviceability • align system-level DFM/EMC/thermal reliability requirements in early phase and guide downstream teams with clear targets • lead the creation of architecture decks, system requirements, platform-level block diagrams, and BoM-level feasibility plans • drive internal and customer-facing design reviews for architecture alignment and requirement sign-off • maintain issue-tracking and lessons-learned documentation to improve future concept efficiency