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Quest Defense Systems & Solutions logo
Quest Defense Systems & Solutions

At QDSS, we are more than an engineering company—we are a force for innovation and positive change. With over 25 years of proven expertise in solving mission-critical challenges, we empower our team to push boundaries, combining deep industry knowledge, cutting-edge technology, and a collaborative "think tank" approach. Our vision is to be the trusted partner of choice for our defense and aerospace clients, delivering secure, sustainable, and world-class solutions that build a brighter future.

FPGA Simulation / Verification Engineer

Location

United States

Posted

77 days ago

Salary

$150K - $180K / year

Seniority

Mid Level

No structured requirement data.

Job Description

FPGA Simulation / Verification Engineer

Quest Defense Systems & Solutions

Role Description Unlock the power of Safety- and Mission-Critical Engineering with QDSS. We are seeking exceptional individuals to join our elite team- where your expertise will make an impact that matters. Elevate your career in a company dedicated to excellence and the pursuit of safety and mission success. Quest Defense Systems & Solutions (QDSS) is supporting the verification of a complex aerospace data management platform and is looking for FPGA Simulation / Verification Engineers with strong UVM experience. This role centers on developing and enhancing a SystemVerilog/UVM-based verification environment for safety-critical FPGA designs. You will work alongside a senior verification team to: - Build scalable testbenches - Develop sequences - Debug RTL issues in simulation - Ensure compliance with DO-254 DAL A standards The ideal candidate brings deep hands-on experience in UVM testbench development, strong debugging skills, and a solid understanding of digital design and FPGA verification methodologies. Due to the nature of the project, all applicants must be U.S. citizens. This role is remote with a preference for candidates who live or are willing to relocate to Cedar Rapids, IA. Qualifications - Bachelor's Degree in electrical, computer or software engineering from an accredited college or university - 10+ years of relevant FPGA Verification experience - Ability to construct FPGA Test Bench using UVM Components - Deep experience with System Verilog - Experience with Sequence Development - Experience with developing DO-254 related documents including but not limited to: Test Plans, Test Procedures, Test Cases, Maintaining a Trace Matrix - Troubleshooting RTL Design Flaws using Simulation Environment - Ability to take a problem and come up with a solution - Familiarity with Unit level testbenches - Familiarity with Chip Level testbenches Requirements - Experience developing UVM Predictors and Scoreboards to implement self-checking simulation tests - Familiarity with Register Modeling and Predicting Register Behavior - Proficiency in developing UVM Agents, Drivers, Monitors, and Sequence Items - Experience with Code Coverage Analysis for RTL Source (Statement, Branch, FSM, FSM Transition) Benefits - Competitive pay - Comprehensive medical/dental/life and disability coverage - 401(k) with employer match - Professional development support - Flexible, friendly workplace Full compensation package is based on candidate experience and certifications. Pay ranges from $150,000 to $180,000 USD.

Job Requirements

  • Bachelor's Degree in electrical, computer or software engineering from an accredited college or university
  • 10+ years of relevant FPGA Verification experience
  • Ability to construct FPGA Test Bench using UVM Components
  • Deep experience with System Verilog
  • Experience with Sequence Development
  • Experience with developing DO-254 related documents including but not limited to: Test Plans, Test Procedures, Test Cases, Maintaining a Trace Matrix
  • Troubleshooting RTL Design Flaws using Simulation Environment
  • Ability to take a problem and come up with a solution
  • Familiarity with Unit level testbenches
  • Familiarity with Chip Level testbenches
  • Experience developing UVM Predictors and Scoreboards to implement self-checking simulation tests
  • Familiarity with Register Modeling and Predicting Register Behavior
  • Proficiency in developing UVM Agents, Drivers, Monitors, and Sequence Items
  • Experience with Code Coverage Analysis for RTL Source (Statement, Branch, FSM, FSM Transition)

Benefits

  • Competitive pay
  • Comprehensive medical/dental/life and disability coverage
  • 401(k) with employer match
  • Professional development support
  • Flexible, friendly workplace
  • Full compensation package is based on candidate experience and certifications. Pay ranges from $150,000 to $180,000 USD.

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