• Perform investigations into detected threats using EDR, Network, and Identity telemetry to analyze, contain, and remediate threats in customer environments • Identify, scope, and manage ongoing customer incidents, developing remediation plans, and providing customers with thorough, clear reports of actions taken • Identify effective response strategies and innovative uses for existing tools to enhance customers' security posture, maximize efficiency, and minimize vulnerability • Collaborate with Detection Engineering, Intelligence, Research, and Product Management teams to develop new approaches to threat remediation and provide strategic insights for product improvement • Participate in an on-call rotation to provide 24x7 response and remediation coverage

• Architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC designs • Lead DFT architecture, implementation, verification, and sign-off for complex ASIC and SoC designs • Drive scan architecture, scan insertion, scan chain stitching, and scan compression workflows to achieve high coverage and robust testability • Own MBIST/LBIST integration, implementation, verification, and debug across design and silicon bring-up phases • Perform DFT debug, failure analysis, root-cause investigation, and fault coverage closure for complex silicon issues • Develop and validate DFT constraints, including DFT SDC, timing checks, and DFT-specific timing analysis • Collaborate with RTL design, verification, physical design, STA, and silicon validation teams to resolve integration and implementation issues • Support ATPG pattern generation, ATPG simulations, DRC analysis, test coverage analysis, and diagnosis/debug • Work on JTAG, boundary scan, iJTAG, SSN, and IP-level DFT integration • Review RTL, synthesis, LEC, and physical design impacts on DFT implementation and test quality • Act as a technical escalation point for advanced DFT and post-silicon debug issues • Mentor junior and mid-level DFT engineers and promote best practices in DFT methodology and automation • Develop scripts and automation using TCL, PERL, or Python to improve flow efficiency and debug productivity

Role Description Motional is seeking a Staff Front End Engineer expert for its Web Visualization Tooling team. This role will directly contribute through the creation of critical web tooling and visualization that allows us to improve our feedback loops for machine learning (ML) engineers and improve the performance and adaptability of our autonomous vehicle (AV) system. - Drive cross-team standards and best practices for web development - Own cross team collaboration, ensuring deliveries are made on time and effectively - Architect and scale a modern frontend ecosystem using React, TypeScript, and Vue - Collaborate closely with ML, frontend, UX, data services, data mining, and data annotation teams to align tooling with real-world workflows - Build mission-critical UI systems used by a variety of internal customers - Design initiative experiences for complex, data-heavy workflows - Drive best practices around performance, scalability and maintainability - Ship quickly and iterate in a product driven environment Qualifications - Desire to design and build user-facing visual applications, and a passion for good UX - Strong proficiency in React, Typescript and modern frontend architecture - Proficiency in Vue - Strong product sense with a focus on UX and usability - Ability to work with high ownership and autonomy - Ability to work autonomously and independently, and to drive development initiatives with little oversight - High aptitude for learning and organization skills - Great interpersonal skills and ability to mentor and (on occasion) delegate to other engineers at various levels of relative seniority - A well-established technical design and documentation habit - Capability to work directly with customers to identify foundational needs and provide solutions Requirements - Demonstrated project management expertise / advanced hands-on understanding of project management agility and operational excellence (Bonus Points) - A love for the continuous delivery of value (Bonus Points) - Exposure to backend systems (Node, Python) (Bonus Points) - Experience in Game Development or 3D Visualization (Bonus Points) Benefits - Motional’s benefits include but are not limited to medical, dental, vision, 401k with a company match, health saving accounts, life insurance, pet insurance, and more Company Description Motional is a driverless technology company making autonomous vehicles a safe, reliable, and accessible reality. We’re driven by something more. - Our journey is always people first - We aren't just developing driverless cars; we're creating safer roadways, more equitable transportation options, and making our communities better places to live, work, and connect - Our team is made up of engineers, researchers, innovators, dreamers and doers, who are creating a technology with the potential to transform the way we move - We’re creating first-of-its-kind technology that will transform transportation - We believe in building a great place to work through a progressive, global culture that is diverse, inclusive, and ensures people feel valued at every level of the organization - Diversity helps us to see the world differently; it’s not only good for our business, it’s the right thing to do - Our team is behind some of the industry's largest leaps forward, including the first fully-autonomous cross-country drive in the U.S, the launch of the world's first robotaxi pilot, and operation of the world's longest-standing public robotaxi fleet - Formed as a joint venture between Hyundai Motor Group and Aptiv, Motional is fundamentally changing how people move through their lives - Headquartered in Boston, Motional has operations in the U.S and Asia

Role Description We are seeking a highly experienced Lead ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC designs. This role requires deep technical ownership across DFT architecture, scan insertion, ATPG, MBIST/LBIST, JTAG, boundary scan, and post-silicon validation, along with the ability to lead cross-functional debug efforts and drive resolution of critical silicon issues. The ideal candidate will have strong hands-on expertise in DFT fundamentals, fault models, test coverage, diagnosis, and debug, as well as the ability to evaluate and adopt emerging DFT methodologies and architecture schemes to improve robustness, quality, and yield. Key Responsibilities - Lead DFT architecture, implementation, verification, and sign-off for complex ASIC and SoC designs. - Drive scan architecture, scan insertion, scan chain stitching, and scan compression workflows to achieve high coverage and robust testability. - Own MBIST/LBIST integration, implementation, verification, and debug across design and silicon bring-up phases. - Perform DFT debug, failure analysis, root-cause investigation, and fault coverage closure for complex silicon issues. - Develop and validate DFT constraints, including DFT SDC, timing checks, and DFT-specific timing analysis. - Collaborate with RTL design, verification, physical design, STA, and silicon validation teams to resolve integration and implementation issues. - Support ATPG pattern generation, ATPG simulations, DRC analysis, test coverage analysis, and diagnosis/debug. - Work on JTAG, boundary scan, iJTAG, SSN, and IP-level DFT integration. - Review RTL, synthesis, LEC, and physical design impacts on DFT implementation and test quality. - Act as a technical escalation point for advanced DFT and post-silicon debug issues. - Mentor junior and mid-level DFT engineers and promote best practices in DFT methodology and automation. - Develop scripts and automation using TCL, PERL, or Python to improve flow efficiency and debug productivity. Qualifications - Strong hands-on experience in ASIC DFT with end-to-end ownership. - Solid understanding of DFT fundamentals, fault models, test techniques, and test coverage concepts. - Deep expertise in scan architecture, ATPG, MBIST, LBIST, JTAG, boundary scan, and silicon debug. - Hands-on experience with Synopsys, Cadence, and Siemens/Mentor EDA tools. - Proven experience in scan insertion, ATPG setup, simulation, debug, and DRC analysis. - Experience with MBIST implementation and verification; SMS experience preferred. - Experience with scan architecture and scan chain stitching; Tessent/SSN experience preferred. - Strong understanding of PLLs, RTL design, synthesis flows, logical equivalence checking (LEC), and physical design implementation. - Proven post-silicon debug and silicon bring-up experience. - Exposure to large SoC designs, hierarchical DFT flows, and multi-domain integration challenges. - Strong communication skills and the ability to work independently with minimal ramp-up. Preferred Experience - MBIST post-silicon validation. - ATPG simulations and fault coverage debug. - DFT RTL, DFD, DFT verification, and IP-level DFT integration. - DFT SDC creation and DFT timing closure support. - Boundary scan, iJTAG, SSN, and design-for-debug methodologies. - TCL/PERL scripting for DFT automation, reporting, and debug. - Experience working across multiple ASIC technology nodes and complex product development cycles. - Familiarity with yield learning, diagnosis, and manufacturing test optimization.