This description is a summary of our understanding of the job description. Click on 'Apply' button to find out more. Role Description We are looking for an experienced ASIC Verification Engineer to support the verification of advanced AI-accelerated ASIC designs used in next-generation hardware platforms. This role focuses heavily on ARM-based IP verification and requires strong experience validating complex SoC components in advanced silicon environments. The selected candidate will work closely with a global engineering team responsible for ensuring the reliability and performance of high-efficiency silicon designs used in cutting-edge hardware technologies. Key Responsibilities - Lead and execute verification activities for ARM-based IP blocks within complex ASIC/SoC designs. - Develop and maintain verification environments using System Verilog and UVM methodologies. - Create and execute test plans, test cases, and regression suites to validate design functionality. - Perform coverage analysis, debugging, and verification closure activities. - Participate in design and architecture reviews related to ARM CPU, GPU, and debug components. - Implement and maintain constraint-random and assertion-based verification techniques. - Support gate-level simulation (GLS) and verification across multiple stages of the development lifecycle. - Collaborate with cross-functional teams including design, architecture, and software teams to resolve issues and improve product quality. - Contribute to improving verification processes, methodologies, and best practices across the engineering team. Qualifications - 5+ years of hands-on ASIC/SoC verification experience in semiconductor or hardware design environments. - Strong expertise in System Verilog and UVM verification methodologies. - Solid experience with ARM architecture and related IPs such as Cortex-A processors, Mali GPU, CoreSight, CSS600 or similar components. - Experience with formal verification, assertions, constraint-random verification, and coverage-driven verification. - Familiarity with coverage metrics, coverage analysis, and debugging complex hardware verification issues. - Experience running gate-level simulations and verification performance validation. - Ability to write and maintain C-based test programs for configuring and validating ARM IP blocks. - Strong problem-solving skills and the ability to work independently in a highly technical environment. Preferred Qualifications - Exposure to advanced silicon nodes (5nm or smaller) is a plus. - Experience working in large, distributed engineering teams. - Knowledge of low-power ASIC design verification is advantageous. - French language skills are beneficial but optional. Benefits - Quarterly travel to Paris for approximately 1 week based on project needs. - Must work in EST time zone. - 12 Months Contract. Company Description Join our team at MetaRPO and embark on a journey of growth and innovation.

This description is a summary of our understanding of the job description. Click on 'Apply' button to find out more. Role Description This role involves contributing to the development of AI systems that learn from real-world chip design workflows and engineering expertise. - Perform power analysis across multiple design stages from RTL to GDSII - Identify power inefficiencies and provide feedback to design teams - Develop or improve automated power analysis workflows and pipelines - Support large-scale dataset generation used for power modeling - Apply expertise in low-power design methodologies to analyze chip architectures - Contribute structured technical insights that support AI model training Qualifications - 4+ years of professional experience in semiconductor or silicon design environments - Experience working with RTL-to-GDSII design flows in advanced technology nodes (7nm or below) - Expertise in low-power design and implementation, including power gating and multi-voltage rails - Experience with power analysis tools such as PrimeTime PX or PrimePower - Knowledge of scripting languages such as Python for automation or modeling - Solid understanding of RTL design principles Requirements - Experience with synthesis or Place-and-Route (PnR) flows - Experience analyzing IP blocks for power characteristics - Experience building power estimation models or automation pipelines - Familiarity with data analysis or machine learning workflows in engineering environments Benefits - Contribute engineering expertise to frontier AI research projects - Work at the intersection of semiconductor engineering and artificial intelligence - Flexible remote engagement with competitive compensation - Collaborate on projects that improve AI systems used in chip design workflows Contract Details - Independent contractor role - Fully remote with flexible scheduling - Minimum commitment of approximately 15 hours per week - Weekly payments via Stripe or Wise - Projects may be extended or adjusted depending on performance and demand About the Platform This opportunity is available through a leading AI-driven work platform.

This description is a summary of our understanding of the job description. Click on 'Apply' button to find out more. Role Description This role involves supporting a leading technology company working on advanced AR/VR hardware systems, focusing on ASIC power analysis and optimisation for next-generation products. - Perform PPA optimisation using Fusion Compiler - Conduct RTL and netlist-level power analysis - Post-process and analyse report log files using scripting tools for data extraction and analysis - Setup, run, debug, and analyse reports across ASIC design flows including synthesis, place-and-route, power, and timing - Implement selected blocks at RTL and UPF level - Develop scripts for data analysis and report automation - Document workflows and communicate technical findings clearly Qualifications - 10+ years of experience as an ASIC power engineer, CAD engineer, or physical design engineer - Experience with power estimation tools, synthesis workflows, and physical design flows - Strong understanding of power trade-offs in ASIC design and back-end implementation - Hands-on experience in scripting and data analysis - Experience working with ASIC design flows and power optimisation methodologies - Strong problem-solving and analytical skills - Bachelors degree in Electrical Engineering, Computer Science, or equivalent experience Requirements - Experience with Synopsys tools (DC, ICC, PTPX/PrimePower, VCS, Verdi) or Cadence tools (Joules) - Experience with Python, Perl, or similar scripting tools for data analysis and automation - Experience using Excel or Matlab for modelling, data visualisation, or analysis - Knowledge of low power design methodologies and UPF power intent specifications - Experience with silicon power characterisation or IP/SoC power profiling Benefits - Contribute to the development of next-generation AR/VR hardware systems - Work on advanced ASIC power optimisation and machine learning-enabled device architectures - Collaborate with leading technology teams working on cutting-edge consumer hardware - Apply deep engineering expertise in high-impact semiconductor development projects Contract Details - Full-time role supporting a leading technology company - Remote work with potential collaboration across distributed engineering teams - Competitive compensation between $100–$135 per hour depending on experience - Engagement administered through an enterprise staffing partner - Projects may extend or adjust depending on scope and performance About the Platform This opportunity is available through a leading AI-driven work platform.

This description is a summary of our understanding of the job description. Click on 'Apply' button to find out more. Role Description We are looking for a Senior Mask Layout Engineer on the Fab Tapeout and Validation Team. As a Senior Mask Layout Engineer, you’ll be part of a cross-functional team whose mission is to lead IonQ on its journey to build the world’s best quantum computers to solve the world’s most complex problems. In this role, you will be the owner of full-reticle tapeouts for use in trapped-ion quantum computers, which could include both photonic and analog electronic layers. In addition, you will help develop and maintain the internal PDK and circuit layout libraries, as well as write scripts to automate the layout of masks for tapeouts. You will also have the opportunity to work closely with the photonic and ion trap design and testing teams to help develop new and game-changing quantum technology to enable scalable quantum computing, memory, and networking. The Fab Tapeout and Validation Team is a remote-friendly team and this role can be performed remotely or in-person at IonQ’s College Park, MD or Bothell, WA campuses. - Conduct Python-based layout for full-reticle tapeouts with commercial foundries - Develop and maintain internal component PCell and automated circuit layout libraries - Interface with designers, test engineers, packaging engineers, and foundry team to define layout rules and component designs - Implement physical verification checks of layouts, including DRC and LVS - Develop detailed documentation of tapeouts and lead layout reviews with other team members - Work with cross-functional teams to understand circuit requirements and make recommendations to improve design, layout, and test workflows Qualifications - Bachelor’s degree in Photonics, Physics, Electrical Engineering, or related field, or equivalent practical experience - Knowledge of semiconductor manufacturing processes and techniques - Excellent programming and software skills, including development in an IDE, proficiency with version control software, shell scripting, and code documentation - 2+ years of experience with Python-based mask layout software packages such as Luceda IPKISS, GDSFactory, or Klayout Requirements - M.S. or Ph.D. in Photonics, Physics, Electrical Engineering, or related field - 5+ years experience in generating layout files for complex semiconductor flows with custom elements, such as MEMS, integrated photonics, or superconducting circuits - Past ownership of full-reticle tapeouts with commercial foundries - Experience with commercial simulation, verification, and layout environments such as Synopsys, Cadence, and Ansys - Familiarity with photonic and/or analog electronic device principles including design, test, and fabrication - Proficiency in physical verification including DRC, LVS, and ERC - Experience with semiconductor and/or photonic workflows for tapeout with commercial foundries - Excellent verbal and written communication skills - A meticulous attention to detail and excellent track record of documenting requirements, implementation plan, and tracking progress - Ability to work independently, prioritizing tasks and managing time effectively in a deadline-oriented environment Location The Fab Tapeout and Validation Team is a remote-friendly team and this role can be performed remotely or in-person at IonQ’s College Park, MD or Bothell, WA campuses. Travel Up to 10% Compensation The approximate base salary range for this position is $110,336 - $144,459. The total compensation package includes base, bonus, and equity. Compensation will vary depending on multiple individualized factors, including market location, job-related knowledge, skills, and experience. Benefits - Comprehensive medical, dental, and vision plans - Matching 401K - Unlimited PTO and paid holidays - Parental/adoption leave - Legal insurance - A home internet stipend - Pet insurance Company Description IonQ is developing the world's most powerful full-stack quantum computer based on trapped-ion technology. We are pushing past the limits of classical physics and current supercomputing technology to unlock a new era of computing. Quantum computing has the potential to impact every area of human society for the better. IonQ’s computers will soon redefine industries like medicine, materials science, finance, artificial intelligence, machine learning, cryptography, and more. IonQ is at the forefront of this technological revolution.